Part Number Hot Search : 
5KE110 23990 5ETTT RT09223G 5KP75A PR3000 X100UFG TPL12800
Product Description
Full Text Search
 

To Download UPD70F3079YGF-3BA Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  user?s manual v850/sf1 tm 32-bit single-chip microcontroller hardware pd703078y pd703079y pd70f3079y printed in japan document no. u14665ej2v0um00 (2nd edition) date published april 2001 n cp(k) 1998 ? 2000
2 user?s manual u14665ej2v0um [memo]
user?s manual u14665ej2v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. v850 family and v850/sf1 are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries.
4 user?s manual u14665ej2v0um purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. license not needed: pd70f3079y the customer must judge the need for license: pd703078y, 703079y the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of march, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?
user?s manual u14665ej2v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
6 user?s manual u14665ej2v0um major revisions in this edition (1/2) page description throughout modification of regulator voltage p.31 modification of 1.4 ordering information p.48 modification of description in 2.3 (5) p40 to p47 (port 4) p.49 modification of description in 2.3 (6) p50 to p57 (port 5) p.49 modification of description in 2.3 (7) p60 to p65 (port 6) p.50 modification of description in 2.3 (9) p90 to p96 (port 9) p.53 addition of 2.3 (18) clkout (clock out) p.76 modification of figure 3-12 application of wraparound p.99 addition of caution to 4.4.4 (1) settings and operating states p.102 addition of 4.6 cautions on power save function p.116 modification of 5.2.4 (1) function of p3 pins p.134 modification of figure 5-12 block diagram of p110 and p114 to p117 p.188 addition of 7.8 (1) acknowledgement of interrupt servicing following ei instruction p.195 modification of caution in 8.1.3 (2) capture/compare register n0 (cr00, cr10, cr70) p.196 modification of caution in 8.1.3 (3) capture/compare register n1 (cr01, cr11, cr71) p.221 modification of caution in figure 8-21 control register settings for one-shot pulse output with software trigger p.223 modification of caution in figure 8-23 control register settings for one-shot pulse output with external trigger p.226 modification of figure 8-27 data hold timing of capture register p.226 addition of 8.2.7 (6) (c) one-shot pulse output function p.247 modification of caution in 9.3 (2) watch timer clock selection register (wtncs) p.262 addition of remark to 11.2.2 (1) serial operation mode register n (csimn) p.264 addition of remark to figure 11-3 csimn setting (3-wire serial i/o mode) p.280 addition of 11.3.2 (6) i 2 c0 transfer clock setting method p.281 modification of table 11-3 selection clock setting p.334 addition of remark to 11.4.2 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) p.339 addition of remark to figure 11-29 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) p.364 modification of 12.3 (1) a/d converter mode register 1 (adm1) p.373 addition of description to 12.5 low power consumption mode p.385 modification of figure 15-1 regulator p.386 addition of caution to 16.1 general p.387 deletion of caution from 16.2.1 correction control register (corcn) p.390 addition of caution to chapter 17 flash memory ( pd70f3079y) p.400 modification of description in table 18-1 overview of functions p.402 modification of figure 18-1 block diagram of fcan p.418 modification of figure in 18.4.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31)
user?s manual u14665ej2v0um 7 major revisions in this edition (2/2) page description p.419 modification of bit names in 18.4.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) p.425 modification of description in 18.4.5 can message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) p.429 modification of figure in 18.4.7 can message status registers 00 to 31 (m_stat00 to m_stat31) p.437 addition of caution to 18.4.12 can stop register (cstop) p.439 modification of gom bit description in 18.4.13 can global status register (cgst) p.442 modification of figure 18-2 fcan clocks p.444 modification of description of mfnd4 to mfnd0 bits in 18.4.17 can message search start/result register (cgmss/cgmsr) p.446 addition of caution to 18.4.18 cann address mask a registers l and h (cnmaskla and cnmaskha) p.446 modification of bit names in 18.4.18 cann address mask a registers l and h (cnmaskla and cnmaskha) p.461 modification of bit names in 18.4.25 cann bit rate prescaler register (cnbrp) p.464 modification of caution in 18.4.27 cann synchronization control register (cnsync) p.468 modification of 18.6 time stamp function p.471 modification of description in 18.7 message processing p.472 modification of 18.8 <2> identifier bits set to message buffer 14 (example) p.473 modification of 18.8 <3> mask setting for can module 1 (mask 1) (example) p.488 modification of description in 18.10.7 (1) prescaler p.488 modification of 18.10.7 (2) nominal bit time (8 to 25 time quantum) p.492 modification of figure 18-28 setting of can global interrupt enable register (cgie) p.493 modification of figure 18-30 setting of cann bit rate prescaler register (cnbrp) p.503 modification of 18.11.3 receive setting p.504 modification of figure 18-41 can sleep mode setting p.506 modification of figure 18-44 can stop mode setting p.506 modification of figure 18-45 clearing of can stop mode p.507 modification of 18.12 rules for correct setting of baud rate p.513 modification of 18.14.2 burst read mode p.514 modification of 18.15.2 interrupts that occur for global can interface p.515 addition of 18.17 cautions on use the mark shows major revised points.
8 user?s manual u14665ej2v0um preface readers this manual is intended for users who wish to understand the functions of the v850/sf1 and design application systems using the v850/sf1. purpose this manual is intended to give users an understanding of the hardware functions described in organization below. organization the v850/sf1 user?s manual is divided into two parts: hardware (this manual) and architecture (v850 family tm user?s manual architecture). hardware architecture ? pin functions ? cpu function ? internal peripheral functions ? flash memory programming ? fcan controller ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find out the details of a register whose name is known: refer to appendix a register index . to find out the details of a function, etc., whose name is known: refer to appendix c index . to understand the details of an instruction function: refer to v850 family user?s manual architecture available separately. how to read register formats: names of bits whose numbers are enclosed in a square are defined in the device file under reserved words. to understand the overall functions of the v850/sf1: read this manual in accordance with the contents .
user?s manual u14665ej2v0um 9 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or si gnal name) memory map addresses: higher addresses at the top and lower addresses at the bottom note : footnote for items marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefixes indicating power of 2 (address space, memory capacity): k (kilo) : 2 10 ? 1024 m (mega) : 2 20 ? 1024 2 g (giga) : 2 30 ? 1024 3 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. related documents for v850/sf1 document name document no. v850 family user?s manual architecture u10243e v850/sf1 user?s manual hardware this manual pd703078y, 703079y, 70f3079y data sheet u15183e
10 user?s manual u14665ej2v0um related documents for development tool (user?s manual) document name document no. ie-703002-mc (in-circuit emulator) u11595e ie-703079-mc-em1 (in-circuit emulator option board) to be prepared operation u14568e c language u14566e project manager u14569e ca850 (ver. 2.30 or later) (c compiler package) assembly language u14567e id850 (ver. 2.20 or later) (integrated debugger) operation windows tm based u14580e sm850 (ver.2.20 or later) (system simulator) operation windows based u14782e basics u13430e installation u13410e rx850 (ver. 3.13 or later) (real-time os) technical u13431e basics u13773e installation u13774e rx850 pro (ver. 3.13) (real-time os) technical u13772e rd850 (ver. 3.01) (task debugger) u13737e rd850 pro (ver. 3.01) (task debugger) u13916e az850 (ver.3.0) (system performance analyzer) u14410e pg-fp3 (flash memory programmer) u13502e
user?s manual u14665ej2v0um 11 contents chapter 1 introduction..................................................................................................... ............28 1.1 general................................................................................................................... ....................28 1.2 features .................................................................................................................. ...................29 1.3 applications.............................................................................................................. .................31 1.4 ordering information ...................................................................................................... ..........31 1.5 pin configuration (top view) .............................................................................................. ....32 1.6 function blocks ........................................................................................................... .............35 1.6.1 internal block diagram .................................................................................................. ...................35 1.6.2 internal units.......................................................................................................... ..........................36 chapter 2 pin functions................................................................................................... .............38 2.1 list of pin functions ..................................................................................................... ...........38 2.2 pin states................................................................................................................ ...................45 2.3 description of pin functions.............................................................................................. .....46 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins..............54 2.5 i/o circuit of pins....................................................................................................... ...............56 chapter 3 cpu functions ................................................................................................... ...........58 3.1 features .................................................................................................................. ...................58 3.2 cpu register set .......................................................................................................... ............59 3.2.1 program register set...................................................................................................... ..............60 3.2.2 system register set....................................................................................................... ...............61 3.3 operation modes ........................................................................................................... ...........63 3.4 address space ............................................................................................................. .............64 3.4.1 cpu address space ......................................................................................................... ...........64 3.4.2 images.................................................................................................................... .....................65 3.4.3 wraparound of cpu address space ........................................................................................... 66 3.4.4 memory map................................................................................................................ ................67 3.4.5 area...................................................................................................................... .......................68 3.4.6 external expansion mode ................................................................................................... .........74 3.4.7 recommended use of address space.........................................................................................7 5 3.4.8 peripheral i/o registers .................................................................................................. .............78 3.4.9 specific registers ........................................................................................................ .................85 chapter 4 clock generation function .................................................................................88 4.1 general................................................................................................................... ....................88 4.2 configuration ............................................................................................................. ...............88 4.3 clock output function ..................................................................................................... ........89 4.3.1 control registers ......................................................................................................... .................89 4.4 power save functions ...................................................................................................... .......93 4.4.1 general................................................................................................................... .....................93 4.4.2 halt mode ................................................................................................................. ................94
user?s manual u14665ej2v0um 12 4.4.3 idle mode................................................................................................................. ................. 97 4.4.4 software stop mode........................................................................................................ ......... 99 4.5 oscillation stabilization time ............................................................................................ ... 101 4.6 cautions on power save function....................................................................................... 102 chapter 5 port function ................................................................................................... ........ 104 5.1 port configuration ........................................................................................................ ......... 104 5.2 port pin functions ........................................................................................................ ......... 104 5.2.1 port 0 ................................................................................................................... .................... 104 5.2.2 port 1 ................................................................................................................... .................... 108 5.2.3 port 2 ................................................................................................................... .................... 112 5.2.4 port 3 ................................................................................................................... .................... 115 5.2.5 ports 4 and 5 ............................................................................................................ ............... 118 5.2.6 port 6 ................................................................................................................... .................... 121 5.2.7 ports 7 and 8 ............................................................................................................ ............... 124 5.2.8 port 9 ................................................................................................................... .................... 126 5.2.9 port 10 .................................................................................................................. ................... 129 5.2.10 port 11 ................................................................................................................. .................... 132 5.3 setting when port pin is used for alternate function ....................................................... 136 chapter 6 bus control function.......................................................................................... 1 40 6.1 features .................................................................................................................. ................ 140 6.2 bus control pins and control register ............................................................................... 140 6.2.1 bus control pins .......................................................................................................... .............. 140 6.3 bus access ................................................................................................................ ............. 141 6.3.1 number of access clocks................................................................................................... ....... 141 6.3.2 bus width ................................................................................................................. ................. 142 6.4 memory block function ..................................................................................................... ... 143 6.5 wait function ............................................................................................................. ............ 144 6.5.1 programmable wait function ................................................................................................ ..... 144 6.5.2 external wait function.................................................................................................... ............ 145 6.5.3 relationship between programmable wait and external wait.................................................... 145 6.6 idle state insertion function............................................................................................. .... 146 6.7 bus hold function ......................................................................................................... ........ 147 6.7.1 outline of function....................................................................................................... .............. 147 6.7.2 bus hold procedure ........................................................................................................ .......... 148 6.7.3 operation in power save mode.............................................................................................. ... 148 6.8 bus timing................................................................................................................ .............. 149 6.9 bus priority .............................................................................................................. ............... 156 6.10 memory boundary operation condition.............................................................................. 156 6.10.1 program space ............................................................................................................ ............. 156 6.10.2 data space ............................................................................................................... ................ 156 chapter 7 interrupt/exception processing function................................................. 157 7.1 outline................................................................................................................... .................. 157
user?s manual u14665ej2v0um 13 7.1.1 features .................................................................................................................. ..................157 7.2 non-maskable interrupt.................................................................................................... ......160 7.2.1 operation................................................................................................................. ..................161 7.2.2 restore................................................................................................................... ...................163 7.2.3 np flag................................................................................................................... ....................164 7.2.4 noise eliminator of nmi pin ............................................................................................... ........164 7.2.5 edge detection function of nmi pin ........................................................................................ ...165 7.3 maskable interrupts ....................................................................................................... .........166 7.3.1 operation................................................................................................................. ..................166 7.3.2 restore................................................................................................................... ...................168 7.3.3 priorities of maskable interrupts ......................................................................................... .......169 7.3.4 interrupt control register (xxicn)........................................................................................ ........172 7.3.5 in-service priority register (ispr) ....................................................................................... .......175 7.3.6 interrupt disable flag (id)............................................................................................... ............175 7.3.7 watchdog timer mode register (wdtm) ...................................................................................176 7.3.8 noise elimination ......................................................................................................... ..............176 7.3.9 edge detection function................................................................................................... ..........178 7.4 software exception........................................................................................................ .........179 7.4.1 operation................................................................................................................. ..................179 7.4.2 restore................................................................................................................... ...................180 7.4.3 ep flag................................................................................................................... ....................181 7.5 exception trap ............................................................................................................ ............181 7.5.1 illegal op code definition................................................................................................ ............181 7.5.2 operation................................................................................................................. ..................181 7.5.3 restore................................................................................................................... ...................182 7.6 priority control.......................................................................................................... ..............184 7.6.1 priorities of interrupts and exceptions ................................................................................... ....184 7.6.2 multiple interrupt servicing.............................................................................................. ...........184 7.7 response time ............................................................................................................. ..........187 7.8 periods in which interrupts are not acknowledged...........................................................187 7.9 key interrupt function .................................................................................................... .......190 chapter 8 timer/counter function........................................................................................19 2 8.1 16-bit timer (tm0, tm1, tm7)................................................................................................ 192 8.1.1 outline ................................................................................................................... ....................192 8.1.2 function.................................................................................................................. ...................192 8.1.3 configuration ............................................................................................................. ................194 8.1.4 timer 0, 1, 7 control registers........................................................................................... .........197 8.2 16-bit timer (tm0, tm1, tm7) operation..............................................................................207 8.2.1 operation as interval timer ............................................................................................... .........207 8.2.2 ppg output operation...................................................................................................... ..........209 8.2.3 pulse width measurement ................................................................................................... ......210 8.2.4 operation as external event counter ....................................................................................... ..217 8.2.5 operation as square-wave output ........................................................................................... ..218 8.2.6 operation as one-shot pulse output ........................................................................................ ..220 8.2.7 cautions .................................................................................................................. ..................225 8.3 16-bit timer (tm2 to tm6)................................................................................................... ...230
user?s manual u14665ej2v0um 14 8.3.1 functions ................................................................................................................. ................. 230 8.3.2 configuration ............................................................................................................. ............... 231 8.3.3 timer n control register.................................................................................................. ........... 232 8.4 16-bit timer (tm2 to tm6) operation................................................................................... 237 8.4.1 operation as interval timer ............................................................................................... ........ 237 8.4.2 operation as external event counter....................................................................................... .. 239 8.4.3 operation as square-wave output........................................................................................... .. 240 8.4.4 operation as 16-bit pwm output ............................................................................................ .. 241 8.4.5 cautions .................................................................................................................. ................. 243 chapter 9 watch timer function .......................................................................................... 2 44 9.1 function .................................................................................................................. ................ 244 9.2 configuration............................................................................................................. ............. 245 9.3 watch timer control register .............................................................................................. 246 9.4 operation ................................................................................................................. ............... 248 9.4.1 operation as watch timer.................................................................................................. ........ 248 9.4.2 operation as interval timer ............................................................................................... ........ 249 9.4.3 cautions .................................................................................................................. ................. 250 chapter 10 watchdog timer function ................................................................................ 251 10.1 functions ................................................................................................................ ................ 251 10.2 configuration............................................................................................................ .............. 253 10.3 watchdog timer control register........................................................................................ 25 3 10.4 operation ................................................................................................................ ................ 256 10.4.1 operation as watchdog timer.............................................................................................. ...... 256 10.4.2 operation as interval timer .............................................................................................. ......... 257 10.5 standby function control register...................................................................................... 25 8 chapter 11 serial interface function................................................................................ 259 11.1 overview ................................................................................................................. ................ 259 11.2 3-wire serial i/o (csi0, csi1, csi3) ...................................................................................... 2 59 11.2.1 configuration ........................................................................................................... ................ 260 11.2.2 csin control registers .................................................................................................. ............ 261 11.2.3 operations .............................................................................................................. ................. 263 11.3 i 2 c bus.......................................................................................................................... ........... 266 11.3.1 configuration .......................................................................................................... ................ 269 11.3.2 i 2 c control registers ............................................................................................................ .... 271 11.3.3 i 2 c bus mode functions .......................................................................................................... 2 83 11.3.4 i 2 c bus definitions and control methods ................................................................................. 284 11.3.5 i 2 c interrupt request (intiic0)................................................................................................ 29 1 11.3.6 interrupt request (intiic0) generation timing and wait control............................................... 309 11.3.7 address match detection method ......................................................................................... .. 310 11.3.8 error detection ........................................................................................................ ................ 310 11.3.9 extension code ......................................................................................................... .............. 310 11.3.10 arbitration .......................................................................................................... ..................... 311
user?s manual u14665ej2v0um 15 11.3.11 wakeup function ........................................................................................................ ...............313 11.3.12 communication reservation.............................................................................................. .........314 11.3.13 cautions ............................................................................................................... .....................318 11.3.14 communication operations............................................................................................... .........319 11.3.15 timing of data communication ........................................................................................... .......321 11.4 asynchronous serial interface (uart0, uart1).................................................................328 11.4.1 configuration ............................................................................................................ .................328 11.4.2 uartn control registers .................................................................................................. ..........330 11.4.3 operations............................................................................................................... ..................335 11.4.4 standby function......................................................................................................... ...............347 11.5 3-wire variable-length serial i/o (csi4)...............................................................................34 8 11.5.1 configuration ............................................................................................................ .................348 11.5.2 csi4 control registers................................................................................................... .............351 11.5.3 operations............................................................................................................... ..................355 chapter 12 a/d converter .................................................................................................. ........360 12.1 function................................................................................................................. ..................360 12.2 configuration ............................................................................................................ ..............362 12.3 control registers........................................................................................................ ............364 12.4 operation ................................................................................................................ .................367 12.4.1 basic operation.......................................................................................................... ................367 12.4.2 input voltage and conversion result...................................................................................... .....369 12.4.3 a/d converter operation mode ............................................................................................. .....370 12.5 low power consumption mode ............................................................................................373 12.6 cautions................................................................................................................. ..................373 chapter 13 dma functions .................................................................................................. .......377 13.1 functions................................................................................................................ .................377 13.2 transfer completion interrupt request................................................................................377 13.3 control registers.......................................................................................................... ..........377 13.3.1 dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) ...............................................377 13.3.2 dma internal ram address registers 0 to 5 (dra0 to dra5)...................................................378 13.3.3 dma byte count registers 0 to 5 (dbc0 to dbc5).....................................................................379 13.3.4 dma start factor expansion register (dmas).............................................................................37 9 13.3.5 dma channel control registers 0 to 5 (dchc0 to dchc5) .......................................................380 13.3.6 start factor settings .................................................................................................... ...............381 chapter 14 reset function ................................................................................................. .......382 14.1 general.................................................................................................................. ...................382 14.2 pin operations ........................................................................................................... .............382 14.3 power-on-clear operation ................................................................................................. ....383 chapter 15 regulator....................................................................................................... ...........385 15.1 outline.................................................................................................................. ....................385 15.2 operation ................................................................................................................ .................385
user?s manual u14665ej2v0um 16 chapter 16 rom correction function ................................................................................ 386 16.1 general .................................................................................................................. .................. 386 16.2 rom correction peripheral i/o registers............................................................................ 387 16.2.1 correction control register (corcn)...................................................................................... .. 387 16.2.2 correction request register (corrq) ...................................................................................... 388 16.2.3 correction address registers 0 to 3 (corad0 to corad3) .................................................... 388 chapter 17 flash memory ( pd70f3079y) ............................................................................. 390 17.1 features ................................................................................................................. ................. 390 17.1.1 erasing unit............................................................................................................. .................. 390 17.1.2 write/read time .......................................................................................................... ............... 391 17.2 writing with flash programmer............................................................................................ 391 17.3 programming environment.................................................................................................. . 391 17.4 communication mode ....................................................................................................... .... 392 17.5 pin connection........................................................................................................... ............ 394 17.5.1 v pp pin ........................................................................................................................... ........... 394 17.5.2 serial interface pin..................................................................................................... ............... 394 17.5.3 reset pin ................................................................................................................ ................ 396 17.5.4 port pin (including nmi) ................................................................................................. ........... 396 17.5.5 other signal pins........................................................................................................ ............... 396 17.5.6 power supply ............................................................................................................. ............... 396 17.6 programming method ....................................................................................................... ..... 397 17.6.1 flash memory control ..................................................................................................... .......... 397 17.6.2 flash memory programming mode........................................................................................... 3 97 17.6.3 selection of communication mode.......................................................................................... .. 398 17.6.4 communication command.................................................................................................... .... 398 17.6.5 resources used........................................................................................................... ............. 399 chapter 18 fcan controller................................................................................................ ... 400 18.1 overview of functions .................................................................................................... ...... 400 18.2 configuration............................................................................................................ .............. 401 18.3 internal registers of fcan controller ................................................................................. 403 18.3.1 configuration of message buffers........................................................................................ .... 403 18.3.2 list of fcan registers .................................................................................................. ........... 404 18.4 control registers ........................................................................................................ ........... 418 18.4.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) ................................. 418 18.4.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) .................................... 419 18.4.3 can message time stamp registers 00 to 31 (m_time00 to m_time31) ............................... 421 18.4.4 can message data registers n0 to n7 (m_datan0 to m_datan7)........................................ 423 18.4.5 can message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) ................................................................. 425 18.4.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31)......................... 427 18.4.7 can message status registers 00 to 31 (m_stat00 to m_stat31)...................................... 429 18.4.8 can status set/clear registers 00 to 31 (sc_stat00 to sc_stat31)................................... 431 18.4.9 can interrupt pending register (ccintp) ............................................................................... 43 3 18.4.10 can global interrupt pending register (cgintp)..................................................................... 434
user?s manual u14665ej2v0um 17 18.4.11 cann interrupt pending register (cnintp)............................................................................... .435 18.4.12 can stop register (cstop) .............................................................................................. ........437 18.4.13 can global status register (cgst) ...................................................................................... .....438 18.4.14 can global interrupt enable register (cgie) ............................................................................ .440 18.4.15 can main clock select register (cgcs).................................................................................. ..441 18.4.16 can time stamp count register (cgtsc).................................................................................. 443 18.4.17 can message search start/result register (cgmss/cgmsr) ..................................................444 18.4.18 cann address mask a registers l and h (cnmaskla and cnmaskha).................................446 18.4.19 cann control register (cnctrl)......................................................................................... ......448 18.4.20 cann definition register (cndef) ....................................................................................... ......452 18.4.21 cann information register (cnlast) ..................................................................................... ...455 18.4.22 cann error count register (cnerc) ...................................................................................... ....456 18.4.23 cann interrupt enable register (cnie).................................................................................. .....457 18.4.24 cann bus active register (cnba) ........................................................................................ ......459 18.4.25 cann bit rate prescaler register (cnbrp)............................................................................... ..460 18.4.26 cann bus diagnostic information register (cndinf).................................................................463 18.4.27 cann synchronization control register (cnsync) ....................................................................464 18.5 cautions regarding bit set/clear function .........................................................................466 18.6 time stamp function ...................................................................................................... .......468 18.7 message processing ....................................................................................................... .......471 18.8 mask function............................................................................................................ .............472 18.9 protocol ................................................................................................................. ..................474 18.9.1 protocol mode function................................................................................................... ...........474 18.9.2 message formats.......................................................................................................... .............475 18.10 functions ............................................................................................................... .................484 18.10.1 determination of bus priority .......................................................................................... ...........484 18.10.2 bit stuffing........................................................................................................... .......................484 18.10.3 multiple masters ....................................................................................................... .................484 18.10.4 multi-cast ............................................................................................................. ......................484 18.10.5 can sleep mode/can stop mode function ...............................................................................485 18.10.6 error control function ................................................................................................. ................485 18.10.7 baud rate control function ............................................................................................. ............488 18.11 operations .............................................................................................................. ................491 18.11.1 initialization processing .............................................................................................. ...............491 18.11.2 transmit setting....................................................................................................... ..................502 18.11.3 receive setting........................................................................................................ ..................503 18.11.4 can sleep mode .......................................................................................................... .............504 18.11.5 can stop mode ........................................................................................................... ..............506 18.12 rules for correct setting of baud rate ...............................................................................507 18.13 prioritization of message buffers during receive comparison .......................................510 18.13.1 reception of data frames ................................................................................................ ..........510 18.13.2 reception of remote frames .............................................................................................. ........511 18.14 ensuring data consistency ............................................................................................... ...512 18.14.1 sequential data read .................................................................................................... .............512 18.14.2 burst read mode......................................................................................................... ...............513 18.15 interrupt conditions.................................................................................................... ...........514 18.15.1 interrupts that occur for fcan controller............................................................................... ....514 18.15.2 interrupts that occur for global can interface .......................................................................... .514
user?s manual u14665ej2v0um 18 18.16 how to shut down fcan controller.................................................................................... 515 18.17 cautions on use ......................................................................................................... ........... 515 appendix a register index ................................................................................................. ........ 516 appendix b instruction set list............................................................................................ ... 524 appendix c index ........................................................................................................... .................. 531
user?s manual u14665ej2v0um 19 list of figures (1/6) figure no. title page 3-1 cpu register set .......................................................................................................... ..................................59 3-2 cpu address space......................................................................................................... ...............................64 3-3 images on address space ................................................................................................... ...........................65 3-4 program space............................................................................................................. ...................................66 3-5 data space ................................................................................................................ ......................................66 3-6 memory map ................................................................................................................ ....................................67 3-7 internal rom/flash memory area ............................................................................................ .......................68 3-8 internal ram area ......................................................................................................... ..................................70 3-9 internal peripheral i/o area .............................................................................................. ...............................71 3-10 external memory area (when expanded to 64 kb, 256 kb, or 1 mb) ............................................................ 72 3-11 external memory area (when expanded to 4 mb)............................................................................. .............73 3-12 application of wraparound ................................................................................................. .............................76 3-13 recommended memory map (flash memory version) ............................................................................ .......77 4-1 clock generator........................................................................................................... ....................................88 4-2 oscillation stabilization time............................................................................................ .............................101 5-1 block diagram of p00 to p07............................................................................................... ..........................107 5-2 block diagram of p10 and p12.............................................................................................. ........................110 5-3 block diagram of p11 and p13 to p15 ....................................................................................... ...................111 5-4 block diagram of p20 to p25............................................................................................... ..........................114 5-5 block diagram of p26 and p27.............................................................................................. ........................114 5-6 block diagram of p30 to p34............................................................................................... ..........................117 5-7 block diagram of p40 to p47 and p50 to p57................................................................................ ...............120 5-8 block diagram of p60 to p65............................................................................................... ..........................123 5-9 block diagram of p70 to p77 and p80 to p83................................................................................ ...............125 5-10 block diagram of p90 to p96.............................................................................................. ...........................128 5-11 block diagram of p100 to p107............................................................................................ .........................131 5-12 block diagram of p110 and p114 to p117 .................................................................................... ................134 5-13 block diagram of p111 to p113............................................................................................ .........................135 6-1 byte access (8 bits)...................................................................................................... .................................142 6-2 halfword access (16 bits)................................................................................................. .............................142 6-3 word access (32 bits) ..................................................................................................... ..............................142 6-4 memory block .............................................................................................................. ..................................143 6-5 wait control.............................................................................................................. .....................................145 6-6 example of inserting wait states .......................................................................................... ........................145 6-7 bus hold procedure........................................................................................................ ...............................148 6-8 memory read ............................................................................................................... .................................149 6-9 memory write .............................................................................................................. ..................................153
user?s manual u14665ej2v0um 20 list of figures (2/6) figure no. title page 6-10 bus hold timing.......................................................................................................... .................................. 155 7-1 non-maskable interrupt servicing.......................................................................................... ....................... 161 7-2 acknowledging non-maskable interrupt requests ............................................................................. .......... 162 7-3 reti instruction processing ................................................................................................ ......................... 163 7-4 np flag (np).............................................................................................................. ................................... 164 7-5 maskable interrupt servicing .............................................................................................. .......................... 167 7-6 reti instruction processing ............................................................................................... .......................... 168 7-7 example of interrupt nesting .............................................................................................. .......................... 170 7-8 example of servicing interrupt requests simultaneously generated .......................................................... 172 7-9 interrupt disable flag (id)............................................................................................... .............................. 175 7-10 software exception processing ............................................................................................ ........................ 179 7-11 reti instruction processing .............................................................................................. ........................... 180 7-12 ep flag (ep) ............................................................................................................. .................................... 181 7-13 illegal op code .......................................................................................................... ................................... 181 7-14 exception trap processing ................................................................................................ ........................... 182 7-15 reti instruction processing .............................................................................................. ........................... 183 7-16 pipeline operation at interrupt request acknowledgement .................................................................. ....... 187 7-17 key return block diagram................................................................................................. ........................... 191 8-1 block diagram of tm0, tm1, and tm7 ........................................................................................ ................. 193 8-2 control register settings when tmn operates as interval timer............................................................. ... 207 8-3 configuration of interval timer........................................................................................... ........................... 208 8-4 timing of interval timer operation ........................................................................................ ....................... 208 8-5 control register settings in ppg output operation ......................................................................... ............ 209 8-6 control register settings for pulse width measurement with free-running counter and one capture register .................................................................................. ..... 210 8-7 configuration for pulse width measurement with free-running counter .................................................... 211 8-8 timing of pulse width measurement with free-running counter and one capture register (with both edges specified) ............................................................................... ....... 211 8-9 control register settings for measurement of two pulse widths with free-running counter .................... 212 8-10 crn1 capture operation with rising edge specified........................................................................ ........... 213 8-11 timing of pulse width measurement with free-running counter (with both edges specified)................... 213 8-12 control register settings for pulse width measurement with free-running counter and two capture registers ............................................................................ .. 214 8-13 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) ............................................................................. ...... 215 8-14 control register settings for pulse width measurement by restarting ...................................................... . 216 8-15 timing of pulse width measurement by restarting (with rising edge specified)........................................ 216 8-16 control register settings in external event counter mode ................................................................. ......... 217
user?s manual u14665ej2v0um 21 list of figures (3/6) figure no. title page 8-17 configuration of external event counter .................................................................................. .....................218 8-18 timing of external event counter operation (with rising edge specified) .................................................. .218 8-19 control register settings in square-wave output mode ..................................................................... .........219 8-20 timing of square-wave output operation ................................................................................... .................220 8-21 control register settings for one-shot pulse output with software trigger................................................ .221 8-22 timing of one-shot pulse output operation with software trigger .......................................................... ....222 8-23 control register settings for one-shot pulse output with external trigger................................................ ..223 8-24 timing of one-shot pulse output operation with external trigger (with rising edge specified) .................224 8-25 start timing of 16-bit timer register n .................................................................................. .......................225 8-26 timing after changing compare register during timer count operation....................................................22 5 8-27 data hold timing of capture register..................................................................................... ......................226 8-28 operation timing of ovfn flag............................................................................................ .........................227 8-29 block diagram of tm2 to tm6 .............................................................................................. .........................230 8-30 timing of interval timer operation ....................................................................................... .........................237 8-31 timing of external event counter operation (with rising edge specified) .................................................. .239 8-32 square-wave output operation timing ...................................................................................... ..................240 8-33 timing of pwm output ..................................................................................................... .............................242 8-34 start timing of timer n .................................................................................................. ................................243 9-1 block diagram of watch timer.............................................................................................. ........................244 9-2 operation timing of watch timer/interval timer............................................................................ ...............249 9-3 watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) .........................................250 10-1 block diagram of watchdog timer.......................................................................................... ......................251 11-1 block diagram of 3-wire serial i/o....................................................................................... .........................260 11-2 csimn setting (operation stopped mode) ................................................................................... .................263 11-3 csimn setting (3-wire serial i/o mode)................................................................................... .....................264 11-4 timing of 3-wire serial i/o mode ......................................................................................... .........................265 11-5 block diagram of i 2 c0 ............................................................................................................................. ......267 11-6 serial bus configuration example using i 2 c bus..........................................................................................268 11-7 i 2 c0 transfer clock frequency (f scl ) ............................................................................................................281 11-8 pin configuration diagram................................................................................................ .............................283 11-9 i 2 c bus?s serial data transfer timing ............................................................................................ ...............284 11-10 start conditions ......................................................................................................... ....................................284 11-11 address ................................................................................................................. ........................................285 11-12 transfer direction specification........................................................................................ .............................286 11-13 ack signal .............................................................................................................. ......................................287 11-14 stop condition .......................................................................................................... .....................................288
user?s manual u14665ej2v0um 22 list of figures (4/6) figure no. title page 11-15 wait signal............................................................................................................. ....................................... 289 11-16 arbitration timing example.............................................................................................. ............................. 312 11-17 communication reservation timing ........................................................................................ ..................... 315 11-18 timing for accepting communication reservations ......................................................................... ............ 316 11-19 communication reservation flow chart .................................................................................... .................. 317 11-20 master operation flow chart ............................................................................................. ........................... 319 11-21 slave operation flow chart .............................................................................................. ............................ 320 11-22 example of master to slave communication (when 9-clock wait is selected for both master and slave) ...................................................................... . 322 11-23 example of slave to master communication (when 9-clock wait is selected for both master and slave) ...................................................................... . 325 11-24 block diagram of uartn.................................................................................................. ............................ 329 11-25 asimn setting (operation stopped mode).................................................................................. .................. 335 11-26 asimn setting (asynchronous serial interface mode)...................................................................... ............ 336 11-27 asisn setting (asynchronous serial interface mode) ...................................................................... ............ 337 11-28 brgcn setting (asynchronous serial interface mode) ...................................................................... .......... 338 11-29 brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) ................................................ 339 11-30 error tolerance (when k = 16), including sampling errors ................................................................ .......... 341 11-31 format of transmit/receive data in asynchronous serial interface ........................................................ .... 342 11-32 timing of asynchronous serial interface transmit completion interrupt................................................... ... 344 11-33 timing of asynchronous serial interface receive completion interrupt.................................................... ... 345 11-34 receive error timing .................................................................................................... ................................ 346 11-35 block diagram of 3-wire variable-length serial i/o ...................................................................... .............. 349 11-36 when transfer bit length other than 16 bits is set...................................................................... .............. 350 11-37 csim4 setting (operation stopped mode) .................................................................................. ................. 355 11-38 csim4 setting (3-wire variable-length serial i/o mode) .................................................................. .......... 356 11-39 csib4 setting (3-wire variable-length serial i/o mode) .................................................................. ........... 357 11-40 timing of 3-wire variable-length serial i/o mode ........................................................................ ............... 358 11-41 timing of 3-wire variable-length serial i/o mode (when csib4 = 08h) .................................................... 3 59 12-1 block diagram of a/d converter............................................................................................. ...................... 361 12-2 basic operation of a/d converter.......................................................................................... ....................... 368 12-3 relationship between analog input voltage and a/d conversion result..................................................... 369 12-4 a/d conversion by hardware start (with falling edge specified) ........................................................... ..... 371 12-5 a/d conversion by software start ......................................................................................... ....................... 372 12-6 handling of analog input pin ............................................................................................. ........................... 374 12-7 a/d conversion end interrupt generation timing........................................................................... .............. 375 12-8 handling of adcv dd pin ........................................................................................................................... .... 376
user?s manual u14665ej2v0um 23 list of figures (5/6) figure no. title page 13-1 correspondence between dran setting value and internal ram ............................................................... 378 14-1 system reset timing...................................................................................................... ...............................382 15-1 regulator ................................................................................................................ .......................................385 16-1 block diagram of rom correction .......................................................................................... ......................386 16-2 rom correction operation and program flow................................................................................ ..............389 17-1 environment required for writing programs to flash memory ................................................................ .....391 17-2 communication with dedicated flash programmer (uart0) .................................................................... ...392 17-3 communication with dedicated flash programmer (csi0) ..................................................................... ......392 17-4 communication with dedicated flash programmer (csi0 + hs) ..................................................................393 17-5 v pp pin connection example........................................................................................................ .................394 17-6 conflict of signals (serial interface input pin) ......................................................................... ......................395 17-7 malfunction of other device .............................................................................................. ............................395 17-8 conflict of signals (reset pin) .......................................................................................... ..........................396 17-9 procedure for manipulating flash memory.................................................................................. ..................397 17-10 flash memory programming mode........................................................................................... .....................398 17-11 communication command ................................................................................................... .........................398 18-1 block diagram of fcan.................................................................................................... .............................402 18-2 fcan clocks .............................................................................................................. ...................................442 18-3 example of bit setting/clearing operations ............................................................................... ...................466 18-4 16-bit data during write operation....................................................................................... ........................467 18-5 time stamp function setting for message reception (when cxctrl register?s tmr bit = 0) ..................468 18-6 time stamp function setting for message reception (when cxctrl register?s tmr bit = 1) ..................469 18-7 time stamp function setting for message transmission (when m_ctrl register?s ats bit = 1) ............470 18-8 example of message processing ............................................................................................ ......................471 18-9 composition of layers .................................................................................................... ...............................474 18-10 data frame.............................................................................................................. ......................................475 18-11 remote frame............................................................................................................ ...................................476 18-12 start of frame (sof) .................................................................................................... .................................476 18-13 arbitration field (in standard format mode) ............................................................................. ....................477 18-14 arbitration field (in extended format mode) ............................................................................. ....................477 18-15 control field ........................................................................................................... .......................................478 18-16 data field .............................................................................................................. ........................................479 18-17 crc field ............................................................................................................... .......................................479 18-18 ack field................................................................................................................ .......................................480 18-19 end of frame (eof) ...................................................................................................... ................................480
user?s manual u14665ej2v0um 24 list of figures (6/6) figure no. title page 18-20 interframe space ........................................................................................................ .................................. 481 18-21 error frame............................................................................................................. ...................................... 482 18-22 overload frame .......................................................................................................... .................................. 483 18-23 nominal bit time........................................................................................................ ................................... 488 18-24 coordination of data bit synchronization ................................................................................ ..................... 489 18-25 resynchronization ....................................................................................................... ................................. 490 18-26 initialization processing ............................................................................................... ................................. 491 18-27 setting of can main clock select register (cgcs) ........................................................................ ............ 492 18-28 setting of can global interrupt enable register (cgie).................................................................. ............ 492 18-29 setting of can global status register (cgst) ............................................................................ ................ 493 18-30 setting of cann bit rate prescaler register (cnbrp)..................................................................... ............ 493 18-31 setting of cann synchronization control register (cnsync) ............................................................... ...... 494 18-32 setting of cann interrupt enable register (cnie) ........................................................................ ................ 495 18-33 setting of cann definition register (cndef)............................................................................. .................. 496 18-34 setting of cann control register (cnctrl) ............................................................................... ................. 497 18-35 setting of cann address mask a registers l and h (cnmaskla and cnmaskha)................................... 498 18-36 message buffer setting.................................................................................................. ............................... 499 18-37 setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31)............................ 500 18-38 setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) ....................................... 501 18-39 transmit setting........................................................................................................ .................................... 502 18-40 receive setting......................................................................................................... .................................... 503 18-41 can sleep mode setting .................................................................................................. ............................ 504 18-42 clearing of can sleep mode by can bus active status ..................................................................... ........ 504 18-43 clearing of can sleep mode by cpu....................................................................................... .................... 505 18-44 can stop mode setting ................................................................................................... ............................. 506 18-45 clearing of can stop mode............................................................................................... ........................... 506 18-46 cnsync register settings ................................................................................................ ........................... 510 18-47 sequential data read.................................................................................................... ............................... 512
user?s manual u14665ej2v0um 25 list of tables (1/3) table no. title page 1-1 product lineup of v850/sf1................................................................................................ ............................28 2-1 pin i/o buffer power supplies ............................................................................................. ............................38 2-2 pin operating state according to operation mode........................................................................... ...............45 3-1 program registers......................................................................................................... ..................................60 3-2 system register numbers................................................................................................... ............................61 3-3 interrupt/exception table................................................................................................. ................................69 4-1 operating statuses in halt mode ........................................................................................... .......................95 4-2 operating statuses in idle mode ........................................................................................... ........................97 4-3 operating statuses in software stop mode .................................................................................. ..............100 5-1 pin i/o buffer power supplies ............................................................................................. ..........................104 5-2 port 0 alternate function pins ............................................................................................ ...........................105 5-3 port 1 alternate function pins ............................................................................................ ...........................108 5-4 port 2 alternate function pins ............................................................................................ ...........................112 5-5 port 3 alternate function pins ............................................................................................ ...........................115 5-6 alternate function pins of ports 4 and 5 .................................................................................. .....................118 5-7 port 6 alternate function pins ............................................................................................ ...........................121 5-8 alternate function pins of ports 7 and 8 .................................................................................. .....................124 5-9 port 9 alternate function pins ............................................................................................ ...........................126 5-10 port 10 alternate function pins .......................................................................................... ...........................129 5-11 port 11 alternate function pins .......................................................................................... ...........................132 5-12 setting when port pin is used for alternate function..................................................................... ..............136 6-1 bus control pins .......................................................................................................... ..................................140 6-2 number of access clocks ................................................................................................... ..........................141 6-3 bus priority .............................................................................................................. ......................................156 7-1 interrupt source list ..................................................................................................... .................................158 7-2 interrupt control registers (xxicn) ....................................................................................... .........................174 7-3 priorities of interrupts and exceptions ................................................................................... ........................184 7-4 description of key return detection pin ................................................................................... ....................190 8-1 configuration of timers 0, 1, and 7 ....................................................................................... ........................194 8-2 valid edge of tin0 pin and capture trigger of crn0......................................................................... ...........195 8-3 valid edge of tin1 pin and capture trigger of crn0........................................................................ ............195 8-4 tin0 pin valid edge and crn1 capture trigger.............................................................................. ..............196 8-5 configuration of timers 2 to 6 ............................................................................................. ..........................231
user?s manual u14665ej2v0um 26 list of tables (2/3) table no. title page 9-1 interval time of interval timer ........................................................................................... ........................... 245 9-2 configuration of watch timer .............................................................................................. ......................... 245 9-3 interval time of interval timer ........................................................................................... ........................... 249 10-1 loop detection time of watchdog timer .................................................................................... ................. 252 10-2 interval time of interval timer .......................................................................................... ............................ 252 10-3 watchdog timer configuration ............................................................................................. ........................ 253 10-4 loop detection time of watchdog timer .................................................................................... ................. 256 10-5 interval time of interval timer .......................................................................................... ............................ 257 11-1 configuration of csin.................................................................................................... ................................ 260 11-2 configuration of i 2 c0............................................................................................................................. ........ 269 11-3 selection clock setting .................................................................................................. ............................... 281 11-4 intiic0 generation timing and wait control ............................................................................... ................ 309 11-5 extension code bit definitions........................................................................................... ........................... 310 11-6 status during arbitration and interrupt request generation timing ........................................................ .... 312 11-7 wait periods ............................................................................................................. .................................... 314 11-8 configuration of uartn................................................................................................... ............................. 328 11-9 relationship between main clock and baud rate............................................................................ ............ 340 11-10 receive error causes.................................................................................................... ............................... 346 11-11 configuration of csi4.................................................................................................... ................................ 348 12-1 configuration of a/d converter........................................................................................... .......................... 362 13-1 start factor settings .................................................................................................... ................................. 381 17-1 signal generation of dedicated flash programmer (pg-fp3) ................................................................. .... 393 17-2 pins used by serial interfaces........................................................................................... ........................... 394 17-3 list of communication mode ............................................................................................... ......................... 398 17-4 flash memory control commands ............................................................................................ ................... 399 17-5 response commands ........................................................................................................ .......................... 399 18-1 overview of functions .................................................................................................... .............................. 400 18-2 configuration of message buffers......................................................................................... ........................ 403 18-3 addresses of m_dlcn (n = 00 to 31) ....................................................................................... .................... 418 18-4 addresses of m_ctrln (n = 00 to 31) ...................................................................................... ................... 421 18-5 addresses of m_timen (n = 00 to 31) ...................................................................................... .................... 422 18-6 addresses of m_datanx (n = 00 to 31, x = 0 to 7)......................................................................... .............. 424 18-7 addresses of m_idln and m_idhn (n = 00 to 31) ............................................................................ ............ 426 18-8 addresses of m_confn (n = 00 to 31) ...................................................................................... .................. 428
user?s manual u14665ej2v0um 27 list of tables (3/3) table no. title page 18-9 addresses of m_statn (n = 00 to 31) ...................................................................................... ....................430 18-10 addresses of sc_statn (n = 00 to 31) .................................................................................... ....................432 18-11 addresses of cnmaskla and cnmaskha (a = 0 to 3, n = 1, 2) ............................................................... ...447 18-12 example when adding captured time stamp counter value to last 2 bytes of transmit message..........470 18-13 rtr frame settings ...................................................................................................... ................................477 18-14 protocol mode setting and number of identifier (id) bits................................................................ ..............477 18-15 data length code settings............................................................................................... .............................478 18-16 operation when third bit of intermission is ?dominant (d)? .............................................................. ...........482 18-17 determination of bus priority ........................................................................................... ..............................484 18-18 bit stuffing ............................................................................................................ .........................................484 18-19 types of errors ......................................................................................................... .....................................485 18-20 error frame output timing............................................................................................... .............................485 18-21 types of error statuses ................................................................................................. ................................486 18-22 error counter ........................................................................................................... ......................................487 18-23 prioritization of message buffers when receiving data frames ............................................................. .....510 18-24 prioritization of message buffers when receiving remote frames .......................................................... ...511 b-1 symbols in operand description ............................................................................................ .......................524 b-2 symbols used for op code .................................................................................................. .........................525 b-3 symbols used for operation description.................................................................................... ...................525 b-4 symbols used for flag operation........................................................................................... .......................526 b-5 condition codes ........................................................................................................... .................................526
28 user?s manual u14665ej2v0um chapter 1 introduction the v850/sf1 is a product in nec?s v850 family of single-chip microcontrollers designed for low power operation. 1.1 general the v850/sf1 is a 32-bit single-chip microcontroller that includes the v850 family?s cpu core, and peripheral functions such as rom/ram, a timer/counter, a serial interface, an a/d converter, a dma controller, and features an automotive lan (fcan (full controller area network)). in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850/sf1 has multiplication, saturation operation, and bit manipulation instructions, realized by a hardware multiplier. table 1-1 shows the outline of the v850/sf1 product lineup. table 1-1. product lineup of v850/sf1 product name rom commercial name part number type size ram size i 2 cfcan pd703078y 1 channel pd703079y mask rom v850/sf1 pd70f3079y flash memory 256 kb 16 kb on-chip i 2 c 2 channels
chapter 1 introduction user?s manual u14665ej2v0um 29 1.2 features { number of instructions: 74 { minimum instruction execution time 62.5 ns (operating at 16 mhz, external power supply 5 v, regulator output 3.0 v) { general-purpose registers 32 bits 32 registers { instruction set signed multiplication (16 16 32): 125 ns (operating at 16 mhz) (able to execute instructions in parallel continuously without creating any register hazards). saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space 16 mb of linear address space (for programs and data) external expandability: expandable to 4 mb memory block allocation function: 2 mb per block programmable wait function idle state insertion function { external bus interface 16-bit data bus (address/data multiplexed) 3 v to 5 v interface enabled bus hold function external wait function { internal memory pd703078y, 703079y (mask rom: 256 kb/ram: 16 kb) pd70f3079y (flash memory: 256 kb/ram: 16 kb) { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 41 sources ( pd703078y) 44 sources ( pd703079y, 70f3079y) software exceptions: 32 sources exception trap: 1 source { i/o lines total: 84 (12 input ports and 72 i/o ports) 3 v to 5 v interface enabled { timer/counter 16-bit timer: 3 channels (tm0, tm1, tm7) 16-bit timer: 5 channels (tm2 to tm6) { watch timer when operating under subsystem or main system clock: 1 channel operation using the subsystem or main system clock is also possible in the idle mode. { watchdog timer 1 channel { serial interface (sio) asynchronous serial interface (uart) clocked serial interface (csi) i 2 c bus interface (i 2 c) 8-/16-bit variable-length serial interface csi/uart: 2 channels csi/i 2 c: 1 channel csi (8-/16-bit valuable): 1 channel dedicated baud rate generator: 3 channels
chapter 1 introduction user?s manual u14665ej2v0um 30 { a/d converter 10-bit resolution: 12 channels { dma controller internal ram internal peripheral i/o: 6 channels { rom correction 4 points modifiable { regulator 4.0 v to 5.5 v input internal 3.0 v ( pd703078y, 703079y) 4.5 v to 5.5 v input internal 3.0 v ( pd70f3079y) { key return function 4 to 8 pins selectable, falling edge fixed { clock generator during main system clock or subsystem clock operation 5-level cpu clock (including slew rate and sub operations) { power-saving functions halt/idle/stop modes { automotive lan 2 channels ( pd703079y, 70f3079y) 1 channel ( pd703078y) { package 100-pin plastic lqfp (fine pitch, 14 14) 100-pin plastic qfp (14 20) { cmos structure all static circuits
chapter 1 introduction user?s manual u14665ej2v0um 31 1.3 applications av equipment example : car audio equipment 1.4 ordering information part number package internal rom pd703078ygc- xxx-8eu pd703078ygf- xxx-3ba note pd703079ygc- xxx-8eu pd703079ygf- xxx-3ba note pd70f3079ygc-8eu pd70f3079ygf-3ba note 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) mask rom mask rom mask rom mask rom flash memory flash memory note under development remarks 1. indicates rom code suffix. 2. romless devices are not provided.
chapter 1 introduction user?s manual u14665ej2v0um 32 1.5 pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) ? pd703078ygc- -8eu ? pd703079ygc- -8eu ? pd70f3079ygc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p01/intp0 p13/si1/rxd0 p14/so1/txd0 p15/sck1/asck0 p100/kr0/to7 p101/kr1/ti70 p102/kr2/ti00 p103/kr3/ti01 p104/kr4/to0 p105/kr5/ti10 p106/kr6/ti11 p107/kr7/to1 gnd2 p110/wait p111 p112 p113 p114/cantx1 p115/canrx1 p02/intp1 p116/cantx2 note 2 p117/canrx2 note 2 p03/intp2 xt1 xt2 p77/ani7 p76/ani6 p75/ani5 p74/ani4 adcgnd adcv dd p73/ani3 p72/ani2 p71/ani1 p70/ani0 p07/intp6 p34/vm45/ti71 p33/ti5/to5 p32/ti4/to4 p31/ti3/to3 p30/ti2/to2 p27 p26 p06/intp5 p25/sck4 p24/so4 p23/si4 p05/intp4/adtrg p22/sck3/asck1 p21/so3/txd1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p80/ani8 p81/ani9 p82/ani10 p83/ani11 p00/nmi gnd0 cpureg v dd0 x2 x1 reset clkout ic/v pp note 1 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 gnd1 p10/si0/sda0 p11/so0 p12/sck0/scl0 p20/si3/rxd1 p96/hldrq p95/hldak p94/astb portgnd p93/dstb p92/r/w p91/uben p90/lben portv dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p04/intp3 notes 1. pd703078y, 703079y: ic pd70f3079y: v pp (connect to gnd0 to gnd2 in normal operation mode). 2 . cantx2 and canrx2 are available only for the pd703079y and 70f3079y.
chapter 1 introduction user?s manual u14665ej2v0um 33 100-pin plastic qfp (14 20) ? pd703078ygf- -3ba ? pd703079ygf- -3ba ? pd70f3079ygf-3ba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p15/sck1/asck0 p100/kr0/to7 p101/kr1/ti70 p102/kr2/ti00 p103/kr3/ti01 p104/kr4/to0 p105/kr5/ti10 p106/kr6/ti11 p107/kr7/to1 gnd2 p110/wait p111 p112 p113 p114/cantx1 p115/canrx1 p02/intp1 p116/cantx2 note 2 p117/canrx2 note 2 p03/intp2 p74/ani4 adcgnd adcv dd p73/ani3 p72/ani2 p71/ani1 p70/ani0 p07/intp6 p34/vm45/ti71 p33/ti5/to5 p32/ti4/to4 p31/ti3/to3 p30/ti2/to2 p27 p26 p06/intp5 p25/sck4 p24/so4 p23/si4 p05/intp4/adtrg 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p75/ani5 p76/ani6 p77/ani7 p80/ani8 p81/ani9 p82/ani10 p83/ani11 p00/nmi gnd0 cpureg v dd0 x2 x1 reset clkout ic/v pp note 1 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p10/si0/sda0 p11/so0 p12/sck0/scl0 p01/intp0 p13/si1/rxd0 p14/so1/txd0 p22/sck3/asck1 p21/so3/txd1 portgnd p20/si3/rxd1 p96/hldrq p95/hldak p94/astb p93/dstb p92/r/w p91/uben p90/lben portv dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p04/intp3 gnd1 xt2 xt1 notes 1. pd703078y, 703079y: ic pd70f3079y: v pp (connect to gnd0 to gnd2 in normal operation mode). 2 . cantx2 and canrx2 are available only for the pd703079y and 70f3079y.
chapter 1 introduction user?s manual u14665ej2v0um 34 pin names a16 to a21: address bus p50 to p57: port 5 ad0 to ad15: address/data bus p60 to p65: port 6 adcgnd: ground for analog p70 to p77: port 7 adcv dd power supply for analog p80 to p83: port 8 adtrg: ad trigger input p90 to p96: port 9 ani0 to ani11: analog input p100 to p107: port 10 asck0, asck1: asynchronous serial clock p110 to p117: port 11 astb: address strobe reset: reset canrx1, canrx2: fcan receive data r/w: read/write status cantx1, cantx2: fcan transmit data rxd0, rxd1: receive data clkout: clock output sck0, sck1, cpureg: regulator control sck3, sck4: serial clock dstb: data strobe scl0: serial clock gnd0, gnd1, sda0: serial data gnd2: ground si0, si1, si3, si4: serial input hldak: hold acknowledge so0, so1, so3, hldrq: hold request so4: serial output ic: internally connected ti00, ti01, ti10, intp0 to intp6: interrupt request from peripherals ti11, ti2 to ti5, kr0 to kr7 : key return ti70, ti71: timer input lben: lower byte enable to0 to to5, to7: timer output nmi: non-maskable interrupt request txd0, txd1: transmit data portgnd: ground for ports uben: upper byte enable portv dd power supply for ports v dd0 : power supply p00 to p07: port 0 vm45: v dd = 4.5 v monitor output p10 to p15: port 1 v pp : programming power supply p20 to p27: port 2 wait: wait p30 to p34: port 3 x1, x2: crystal for main clock p40 to p47: port 4 xt1, xt2: crystal for sub-clock
chapter 1 introduction user?s manual u14665ej2v0um 35 1.6 function blocks 1.6.1 internal block diagram intp0 to intp6 nmi intc ti2/to2 ti3/to3 ti4/to4 ti5/to5 sio so0 si0/sda0 n o t e 3 timer/counter ti00,ti01, ti10,ti11, ti70, ti71 so1/txd0 si1/rxd0 so4 si4 csi0/i 2 c0 csi1/uart0 variable- length csi4 watchdog timer note 1 rom cpu 16 kb multiplier 16 16 32 ram pc 32-bit barrel shifter system registers general-purpose registers 32 bits 32 instruction queue bcu a stb ( p94 ) a16 to a21(p60 to p65) ad0 to ad15 (p40 to p47,p50 to p57) a/d converter ports cg clkout x1 x2 xt1 v dd0 portv dd portgnd gnd1 ani0 to ani11 adcgnd adcv dd adtrg p110 to p117 p100 to p107 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p34 p20 to p27 p10 to p15 p00 to p07 sck0/scl0 n o t e 3 sck1/asck0 sck4 reset xt2 hldak ( p95 ) hldrq ( p96 ) wait ( p110 ) uben ( p91 ) alu 16-bit timer: tm0, tm1, tm7 16-bit timer: tm2 to tm6 to0,to1, to7 dmac: 6 ch watch timer p80 to p83 p90 to p96 gnd2 dstb ( p93 ) r/w ( p92 ) lben ( p90 ) so3/txd1 si3/rxd1 csi3/uart1 sck3/asck1 key return kr0 to kr7 rom correction v pp n o t e 3 regulator cpureg ic n o t e 4 3.0 v vm45 gnd0 fcan cantx1 canrx1 cantx2 n o t e 2 canrx2 n o t e 2 notes 1. pd703078y, 703079y: 256 kb (mask rom) pd70f3079y: 256 kb (flash memory) 2. pd703079y, 70f3079y 3. pd70f3079y 4. pd703078y, 703079y
chapter 1 introduction user?s manual u14665ej2v0um 36 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as the multiplier (16 bits 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (3) rom this consists of a 256 kb mask rom or flash memory mapped to the address space starting at 00000000h. rom can be accessed by the cpu in one clock cycle during instruction fetch. (4) ram this consists of a 16 kb ram mapped to the address space starting at ffffb000h. ram can be accessed by the cpu in one clock cycle during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (6) clock generator (cg) the clock generator includes two types of oscillators; each for main system clock (f xx ) and for subsystem clock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (7) timer/counter an eight-channel 16-bit timer/event counter is equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. (8) watch timer this timer counts the reference time period (0.5 second) for counting the clock (the 32.768 khz subsystem clock or the 8.388 mhz main system clock). at the same time, the watch timer can be used as an interval timer for the main system clock. (9) watchdog timer a watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. this timer can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs, and when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs.
chapter 1 introduction user?s manual u14665ej2v0um 37 (10)serial interface (sio) the v850/sf1 includes four kinds of serial interfaces: asynchronous serial interfaces (uart0, uart1), clocked serial interfaces (csin), an 8-/16-bit variable-length serial interface (csi4), and an i 2 c bus interface (i 2 c0). up to four channels can be used at the same time. two of these channels are switchable between the uart and csi and another one is switchable between csi and i 2 c (n = 0, 1, 3). for uart0 and uart1, data is transferred via the txd0, txd1, rxd0, and rxd1 pins. for csin, data is transferred via the son, sin, and sckn pins. for csi4, data is transferred via the so4, si4, and sck4 pins. for i 2 c0, data is transferred via the sda0 and scl0 pins. for uart and csi4, a dedicated baud rate generator is provided. (11)a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (12)dma controller a six-channel dma controller is equipped. this controller transfers data between the internal ram and on- chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (13)ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function port 0 8-bit i/o nmi, external interrupt, a/d converter trigger port 1 6-bit i/o serial interface port 2 8-bit i/o serial interface port 3 5-bit i/o timer i/o, v dd = 4.5 v monitor output port 4 8-bit i/o external address/data bus port 5 8-bit i/o port 6 6-bit i/o external address bus port 7 8-bit input a/d converter analog input port 8 4-bit input port 9 7-bit i/o external bus interface control signal i/o port 10 8-bit i/o timer i/o, key return input port 11 8-bit i/o general- purpose port wait control, fcan data i/o (14)fcan controller the fcan controller is a small-scale digital data transmission system for transferring data between units. a two-channel fcan controller is incorporated in the pd703079y and 70f3079y (fcan1, fcan2), and a one-channel fcan controller is incorporated in the pd703078y (fcan1).
38 user?s manual u14665ej2v0um chapter 2 pin functions 2.1 list of pin functions the names and functions of pins of v850/sf1 are described below, divided into port pins and non-port pins. there are two types of power supplies for the pin i/o buffers: adcv dd and portv dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins adcv dd port 7, port 8 portv dd port 0, port 1, port 2, port 3, port 4, port 5, port 6, port 9, port 10, port 11, reset, clkout
chapter 2 pin functions user?s manual u14665ej2v0um 39 (1) port pins (1/3) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5 p07 i/o no port 0 8-bit i/o port input/output can be specified in 1-bit units. intp6 p10 si0/sda0 p11 so0 p12 sck0/scl0 p13 si1/rxd0 p14 so1/txd0 p15 i/o no port 1 6-bit i/o port input/output can be specified in 1-bit units. sck1/asck0 p20 si3/rxd1 p21 so3/txd1 p22 sck3/asck1 p23 si4 p24 so4 p25 sck4 p26 ? p27 i/o no port 2 8-bit i/o port input/output can be specified in 1-bit units. ? p30 ti2/to2 p31 ti3/to3 p32 ti4/to4 p33 ti5/to5 p34 i/o no port 3 5-bit i/o port input/output can be specified in 1-bit units. vm45/ti71 p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output can be specified in 1-bit units. ad7 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 40 (2/3) pin name i/o pull function alternate function p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output can be specified in 1-bit units. a21 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 p90 lben p91 uben p92 r/w p93 dstb p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output can be specified in 1-bit units. hldrq remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 41 (3/3) pin name i/o pull function alternate function p100 kr0/to7 p101 kr1/ti7 p102 kr2/ti00 p103 kr3/ti01 p104 kr4/to0 p105 kr5/ti10 p106 kr6/ti11 p107 i/o yes port 10 8-bit i/o port input/output can be specified in 1-bit units. kr7/to1 p110 wait p111 ? p112 ? p113 ? p114 cantx1 p115 canrx1 p116 cantx2 note p117 i/o no port 11 8-bit i/o port input/output can be specified in 1-bit units. canrx2 note note only for the pd703079y, 70f3079y remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 42 (2) non-port pins (1/3) pin name i/o pull function alternate function a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p50 to p57 adcgnd ? ? ground potential for a/d converter ? adcv dd ? ? power supply pin and reference voltage pin for a/d converter ? adtrg input no a/d converter external trigger input p05/intp4 ani0 to ani7 p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 p15/sck1 asck1 input no baud rate clock input for uart0 and uart1 p22/sck3 astb output no external address strobe signal output p94 canrx1 input can1 receive data i nput p115 canrx2 input can2 receive data input ( pd703079y and 70f3079y only) p117 cantx1 output can1 transmit data output p114 cantx2 output no can2 transmit data output ( pd703079y and 70f3079y only) p116 clkout output ? internal system clock output ? cpureg ? ? connection of regulator output stabilizing capacitance ? dstb output no external data strobe signal output p93 gnd0 to gnd2 ?? ground potential ? hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 ic ?? internally connected ( pd703078y and 703079y only) ? intp0 to intp3 external interrupt request input (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 external interrupt request input (digital noise elimination) p06 intp6 input yes external interrupt request input (digital noise elimination for remote control) p07 kr0 p100/to7 kr1 p101/ti70 kr2 p102/ti00 kr3 p103/ti01 kr4 p104/to0 kr5 p105/ti10 kr6 p106/ti11 kr7 input yes key return input p107/ti01 lben output no external data bus?s lower byte enable signal output p90 nmi input no non-maskable interrupt request input p00 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 43 (2/3) pin name i/o pull function alternate function portgnd ? ? ground potential for port output ? portv dd ? ? positive power supply for port output ? reset input ? system reset input ? r/w output no external read/write status output p92 rxd0 p13/si1 rxd1 input no serial receive data input for uart0 and uart1 p20/si3 sck0 p12/scl0 sck1 p15/asck0 sck3 serial clock i/o (3-wire type) for csi0, csi1, csi3 p22/asck1 sck4 i/o no serial clock i/o for variable-length csi4 (3-wire type) p25 scl0 i/o no serial clock i/o for i 2 c0 p12/sck0 sda0 i/o no serial transmit/receive data i/o for i 2 c0 p10/si0 si0 p10/sda0 si1 p13/rxd0 si3 serial receive data input (3-wire type) for csi0, csi1, csi3 p20/rxd1 si4 input no serial receive data input (3-wire type) for variable-length csi4 p23 so0 p11 so1 p14/txd0 so3 serial transmit data output (3-wire type) for csi0, csi1, csi3 p21/txd1 so4 output no serial transmit data output for variable-length csi4 (3-wire type) p24 ti00 shared as external capture trigger input and external count clock input for tm0 p102/kr2 ti01 external capture trigger input for tm0 p103/kr3 ti10 external count clock input/external capture trigger input for tm1 p105/kr5 ti11 yes external capture trigger input for tm1 p106/kr6 ti2 external count clock input for tm2 p30/to2 ti3 external count clock input for tm3 p31/to3 ti4 external count clock input for tm4 p32/to4 ti5 no external count clock input for tm5 p33/to5 ti70 yes external count clock input/external capture trigger input for tm7 p101/kr1 ti71 input no external capture trigger input for tm7 p34/vm45 to0 pulse signal output for tm0 p104/kr4 to1 yes pulse signal output for tm1 p107/kr7 to2 pulse signal output for tm2 p30/ti2 to3 pulse signal output for tm3 p31/ti3 to4 pulse signal output for tm4 p32/ti4 to5 no pulse signal output for tm5 p33/ti5 to7 output yes pulse signal output for tm7 p100/kr0 remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 44 (3/3) pin name i/o pull function alternate function txd0 p14/so1 txd1 output no serial transmit data output for uart0 and uart1 p21/so3 uben output no higher byte enable signal output for external data bus p91 v dd0 ?? positive power supply pin ? vm45 output no v dd = 4.5 v monitor output p34/ti71 v pp ?? high-voltage apply pin for program write/verify ( pd70f3079y only) ? wait input yes control signal input for inserting wait in bus cycle p110 x1 input ? x2 ? no resonator connection for main clock ? xt1 input ? xt2 ? no resonator connection for subsystem clock ? remark pull: on-chip pull-up resistor
chapter 2 pin functions user?s manual u14665ej2v0um 45 2.2 pin states the operating states of various pins are described below with reference to the operation mode. table 2-2. pin operating state according to operation mode operation mode pin reset stop mode idle mode halt mode bus hold idle state ad0 to ad15 hi-z hi-z hi-z hi-z hi-z hi-z a16 to a21 hi-z hi-z hi-z held hi-z held lben, uben hi-z hi-z hi-z held hi-z held r/w hi-z hi-z hi-z h hi-z h dstb hi-z hi-z hi-z h hi-z h astb hi-z hi-z hi-z h hi-z h hldrq ??? operating operating operating hldak hi-z hi-z hi-z operating l operating wait ?????? clkout hi-z l l operating note operating note operating note note low level (l) when in clock output inhibit mode remark hi-z: high impedance held: state is held during previously set external bus cycle l: low-level output h: high-level output ? : input not sampled
chapter 2 pin functions user?s manual u14665ej2v0um 46 2.3 description of pin functions (1) p00 to p07 (port 0) ??? 3-state i/o port 0 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p00 to p07 can function as i/o port pins and can also function as nmi inputs, external interrupt request inputs, and external triggers for the a/d converter. port/control mode can be selected for each bit, and the pin?s valid edge is specified by the egp0 and egn0 registers. (a) port mode p00 to p07 can be set to input or output in 1-bit units according to the contents of the port 0 mode register (pm0). (b) control mode (i) nmi (non-maskable interrupt request) ??? input this is a non-maskable interrupt request signal input pin. (ii) intp0 to intp6 (interrupt request from peripherals) ??? input these are external interrupt request input pins. (iii) adtrg (ad trigger input) ??? input this is the a/d converter?s external trigger input pin. this pin is controlled by a/d converter mode register 1 (adm1). (2) p10 to p15 (port 1) ??? 3-state i/o port 1 is a 6-bit i/o port in which input and output can be specified in 1-bit units. p10 to p15 can function as i/o port pins and can also operate as input or output pins for the serial interface. port/control mode can be selected for each bit. p10 and p12 can be selected as normal output or n-ch open-drain output. (a) port mode p10 to p15 can be set to input or output in 1-bit units according to the contents of the port 1 mode register (pm1). (b) control mode (i) si0, si1 (serial input 0, 1) ??? input these are the serial receive data input pins of csi0 and csi1. (ii) so0, so1 (serial output 0, 1) ??? output these are the serial transmit data output pins of csi0 and csi1. (iii) sck0, sck1 (serial clock 0, 1) ??? 3-state i/o these are the serial clock i/o pins for csi0 and csi1. (iv) sda0 (serial data 0) ??? i/o this is the serial transmit/receive data i/o pin for i 2 c0.
chapter 2 pin functions user?s manual u14665ej2v0um 47 (v) scl0 (serial clock 0) ??? i/o this is the serial clock i/o pin for i 2 c0. (vi) rxd0 (receive data 0) ??? input this is the serial receive data input pin of uart0. (vii) txd0 (transmit data 0) ??? output this is the serial transmit data output pin of uart0. (viii) asck0 (asynchronous serial clock 0) ??? input this is the serial baud rate clock input pin of uart0. (3) p20 to p27 (port 2) ??? 3-state i/o port 2 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p20 to p27 can function as i/o port pins and input or output pins for the serial interface. port/control mode can be selected for each bit. (a) port mode p20 to p27 can be set to input or output in 1-bit units according to the contents of the port 2 mode register (pm2). (b) control mode (i) si3, si4 (serial input 3, 4) ??? input these are the serial receive data input pins of csi3 and csi4. (ii) so3, so4 (serial output 3, 4) ??? output these are the serial transmit data output pins of csi3 and csi4. (iii) sck3, sck4 (serial clock 3, 4) ??? 3-state i/o these are the serial clock i/o pins of csi3 and csi4. (iv) rxd1 (receive data 1) ... input this is the serial receive data input pin of uart1. (v) txd1 (transmit data 1) ... output this is the serial transmit data output pin of uart1. (vi) asck1 (asynchronous serial clock 1) ... input this is the serial baud rate clock input pin of uart1.
chapter 2 pin functions user?s manual u14665ej2v0um 48 (4) p30 to p34 (port 3) ??? 3-state i/o port 3 is a 5-bit i/o port in which input and output can be specified in 1-bit units. p30 to p34 can function as i/o port pins, input or output pins for the timer/counter, and v dd = 4.5 v monitor output. port/control mode can be selected for each bit. (a) port mode p30 to p34 can be set to input or output in 1-bit units according to the contents of the port 3 mode register (pm3). (b) control mode (i) ti2, ti3, ti4, ti5, ti71 (timer input 2, 3, 4, 5, 71) ??? input these are the external count clock input pins of timers 2, 3, 4, 5, and 7. (ii) to2, to3, to4, to5 (timer output 2, 3, 4, 5) ??? output these are the pulse signal output pins of timers 2, 3, 4, and 5. (iii) vm45 (v dd = 4.5 v monitor output) ??? output this is the v dd = 4.5 v monitor output pin. (5) p40 to p47 (port 4) ??? 3-state i/o port 4 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p40 to p47 can function as i/o port pins and as a time division address/data bus (ad0 to ad7) when memory is expanded externally. (a) port mode p40 to p47 can be set to input or output in 1-bit units according to the contents of the port 4 mode register (pm4). (b) control mode (external expansion mode) p40 to p47 can be set as ad0 to ad7 according to the contents of the memory expansion mode register (mm). (i) ad0 to ad7 (address/data 0 to 7) ??? 3-state i/o these pins comprise a multiplexed address/data bus that is used for external access. at the address timing (t1 state), these pins operate as the ad0 to ad7 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the lower 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle as inactive, these pins go into a high-impedance state.
chapter 2 pin functions user?s manual u14665ej2v0um 49 (6) p50 to p57 (port 5) ??? 3-state i/o port 5 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p50 to p57 can function as i/o port pins and as a time division address/data bus (ad8 to ad15) when memory is expanded externally. (a) port mode p50 to p57 can be set to input or output in 1-bit units according to the contents of the port 5 mode register (pm5). (b) control mode (external expansion mode) p50 to p57 can be specified as ad8 to ad15 according to the contents of the memory expansion mode register (mm). (i) ad8 to ad15 (address/data 8 to 15) ??? 3-state i/o these pins comprise a multiplexed address/data bus that is used for external access. at the address timing (t1 state), these pins operate as the ad8 to ad15 (22-bit address) output pins. at the data timing (t2, tw, t3), they operate as the higher 8-bit i/o bus pins for 16-bit data. the output changes in synchronization with the rising edge of the clock in each state within the bus cycle. when the timing sets the bus cycle as inactive, these pins go into a high-impedance state. (7) p60 to p65 (port 6) ??? 3-state i/o port 6 is a 6-bit i/o port in which input and output can be specified in 1-bit units. p60 to p65 can function as i/o port pins and as an address bus (a16 to a21) when memory is expanded externally. during 8-bit access of port 6, the higher 2 bits are ignored when writing, and are read as ?00? when reading. port/control mode can be selected in 2-bit units. (a) port mode p60 to p65 can be set to input or output in 1-bit units according to the contents of the port 6 mode register (pm6). (b) control mode (external expansion mode) p60 to p65 can be set as a16 to a21 according to the contents of the memory expansion mode register (mm). (i) a16 to a21 (address 16 to 21) ??? output these pins comprise an address bus that is used for external access. these pins operate as the higher 6-bit address output pins within a 22-bit address. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s address is retained.
chapter 2 pin functions user?s manual u14665ej2v0um 50 (8) p70 to p77 (port 7), p80 to p83 (port 8) ??? input port 7 is an 8-bit input-only port in which all pins are fixed to input. port 8 is a 4-bit input-only port in which all pins are fixed to input. p70 to p77 and p80 to p83 can function as input ports and as analog input pins for the a/d converter in control mode. however, they cannot be switched between input ports and analog input pins. (a) port mode p70 to p77 and p80 to p83 are input-only pins. (b) control mode p70 to p77 also function as pins ani0 to ani7 and p80 to p83 also function as ani8 to ani11, but these alternate functions are not switchable. (i) ani0 to ani11 (analog input 0 to 11) ??? input these are analog input pins for the a/d converter. connect a capacitor between adcv dd and adcgnd to prevent noise-related operation faults. also, do not apply voltage that is outside the range for adcv dd and adcgnd to pins that are being used as inputs for the a/d converter. if it is possible for noise above the adcv dd range or below the adcgnd to enter, clamp these pins using a diode that has a small v f value. (9) p90 to p96 (port 9) ??? 3-state i/o port 9 is a 7-bit i/o port in which input and output can be specified in 1-bit units. p90 to p96 can function as i/o port pins, control signal output pins, and bus hold control signal output pins when memory is expanded externally. during 8-bit access of port 9, the msb is ignored when writing and is read as ?0? when reading. (a) port mode p90 to p96 can be set to input or output in 1-bit units according to the contents of the port 9 mode register (pm9). (b) control mode (external expansion mode) p90 to p96 can be set to operate as control signal outputs for external memory expansion according to the contents of the memory expansion mode register (mm). (i) lben (lower byte enable) ??? output this is the lower byte enable signal output pin for an external 16-bit data bus. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s status is retained.
chapter 2 pin functions user?s manual u14665ej2v0um 51 (ii) uben (upper byte enable) ??? output this is the higher byte enable signal output pin for an external 16-bit data bus. during byte access of even-numbered addresses, these pins are set as inactive (high level). the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the timing sets the bus cycle as inactive, the previous bus cycle?s status is retained. access uben lben ad0 word access 0 0 0 halfword access 0 0 0 byte access even-numbered address 1 0 0 odd-numbered address 0 1 1 (iii) r/w (read/write status) ??? output this is an output pin for the status signal that indicates whether the bus cycle is a read cycle or write cycle during external access. high level is set during the read cycle and low level is set during the write cycle. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. high level is set when the timing sets the bus cycle as inactive. (iv) dstb (data strobe) ??? output this is an output pin for the external data bus?s access strobe signal. output becomes active (low level) during the t2 and tw states of the bus cycle. output becomes inactive (high level) when the timing sets the bus cycle as inactive. (v) astb (address strobe) ??? output this is an output pin for the external address bus?s latch strobe signal. output becomes active (low level) in synchronization with the falling edge of the clock during the t1 state of the bus cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the t3 state of the bus cycle. output becomes inactive when the timing sets the bus cycle as inactive. (vi) hldak (hold acknowledge) ??? output this is an output pin for the acknowledge signal that indicates high impedance status for the address bus, data bus, and control bus when the v850/sf1 receives a bus hold request. the address bus, data bus, and control bus are set to high impedance when this signal is active. (vii) hldrq (hold request) ??? input this is the input pin by which an external device requests the v850/sf1 to release the address bus, data bus, and control bus. this pin can be input asynchronously to clkout. when this pin is active, the address bus, data bus, and control bus are set to high impedance. this occurs either when the v850/sf1 completes execution of the current bus cycle or immediately if no bus cycle is being executed. the hldak signal is then set as active and the bus is released.
chapter 2 pin functions user?s manual u14665ej2v0um 52 (10) p100 to p107 (port 10) ??? 3-state i/o port 10 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p100 to p107 can function as i/o port pins, timer/counter i/o pins, and key return input pins. (a) port mode p100 to p107 can be set to input or output in 1-bit units according to the contents of the port 10 mode register (pm10). (b) control mode (i) kr0 to kr7 (key return 0 to 7) ... input these are key interrupt input pins. their operations are specified by the key return mode register (krm). (ii) ti00, ti01, ti10, ti11, ti70 (timer input 00, 01, 10, 11, 70) ... input these are external count clock input pins for timers 0, 1, and 7. (iii) to0, to1, to7 (timer output 0, 1, 7) ... output these are pulse signal output pins for timers 0, 1, and 7. (11) p110 to p117 (port 11) ??? 3-state i/o port 11 is an 8-bit i/o port in which input and output can be specified in 1-bit units. p110 to p117 can function as i/o port pins, fcan data i/o pins, and the control signal (wait) that inserts waits into the bus cycle. (a) port mode p110 to p117 can be set to input or output in 1-bit units according to the contents of the port 11 mode register (pm11). (b) control mode (i) wait (wait) ??? input this is an input pin for the control signal used to insert waits into the bus cycle. this pin is sampled at the falling edge of the clock during the t2 or tw state of the bus cycle. on/off switching of the wait function is performed by the port alternate function control register (pac). (ii) canrx1, canrx2 (can receive data 1, 2) ??? input these are data input signals for can1 and can2. canrx2 is available only for the pd703079y and 70f3079y. (iii) cantx1, cantx2 (can transmit data 1, 2) ??? output these are data output signals for can1 and can2. cantx2 is available only for the pd703079y and 70f3079y.
chapter 2 pin functions user?s manual u14665ej2v0um 53 (12) reset (reset) ??? input reset input is an asynchronous input signal and has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/start operations, this pin can also be used to cancel a standby mode (halt, idle, or stop mode). (13) x1, x2 (crystal) these pins are used to connect the resonator that generates the main clock. (14) xt1, xt2 (crystal for sub-clock) these pins are used to connect the resonator that generates the subclock. (15) adcv dd (analog power supply) this is the analog positive power supply pin for the a/d converter and alternate-function ports. (16) adcgnd (ground for analog) this is the ground pin for the a/d converter and alternate-function ports. (17) cpureg (regulator control) this is the regulator pin for the cpu power supply. connect this pin to gnd0 to gnd2 via a capacitor of 1 f (recommended value). (18) clkout (clock out) ??? output this pin outputs the bus clock generated internally. (19) portv dd (power supply for ports) this is the positive power supply pin for i/o ports and alternate-function pins. (20) portgnd (ground for ports) this is the ground pin for i/o ports and alternate-function pins (except for the alternate-function ports of the bus interface). (21) v dd0 (power supply) this is the positive power supply pin. all v dd0 pins should be connected to a positive power supply. (22) gnd0 to gnd2 (ground) these are the ground pins. all gnd0 to gnd2 pins should be grounded. (23) v pp (programming power supply) this is the positive power supply pin used for flash memory programming mode. this pin is used in the pd70f3079y. connect to gnd0 to gnd2 in normal operation mode. (24) ic (internally connected) this is an internally connected pin used in the pd703078y and 703079y. connect directly to gnd0 to gnd2 in normal operation mode.
chapter 2 pin functions user?s manual u14665ej2v0um 54 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins (1/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection method p00 nmi portv dd p01 to p04 intp0 to intp3 p05 intp4/adtrg p06, p07 intp5, intp6 8 p10 si0/sda0 10 p11 so0 5 p12 sck0/scl0 10 p13 si1/rxd0 8 p14 so1/txd0 5 p15 sck1/asck0 8 portv dd p20 si3/rxd1 8 p21 so3/txd1 5 p22 sck3/asck1 p23 si4 8 p24 so4 5 p25 sck4 p26 ? 8 p27 ? 5 portv dd p30 to p33 ti2/to2 to ti5/to5 portv dd p34 vm45/ti71 8 p40 to p47 ad0 to ad7 5 portv dd p50 to p57 ad8 to ad15 5 portv dd p60 to p65 a16 to a21 5 portv dd input: independently connect to portv dd or portgnd via a resistor. output: leave open. p70 to p77 ani0 to ani7 9 adcv dd p80 to p83 ani8 to ani11 9 adcv dd independently connect to adcv dd or adcgnd via a resistor. p90 lben portv dd p91 uben p92 r/w p93 dstb p94 astb p95 hldak p96 hldrq 5 input: independently connect to portv dd or portgnd via a resistor. output: leave open.
chapter 2 pin functions user?s manual u14665ej2v0um 55 (2/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection method p100 kr0/to7 p101 kr1/ti70 p102 kr2/ti00 p103 kr3/ti01 p104 kr4/to0 p105 kr5/ti10 p106 kr6/ti11 p107 kr7/to1 8-a portv dd p110 w ait p111 to p113 ? 5 p114 cantx1 5 p115 canrx1 8 p116 cantx2 note 1 5 p117 canrx2 note 1 8 portv dd input: independently connect to portv dd or portgnd via a resistor. output: leave open. clkout ? 4portv dd leave open. reset ? 2portv dd ? x1 ??? ? x2 ??? ? xt1 ? ? ? connect to gnd0 to gnd2 via a resistor. xt2 ? ? ? leave open. v pp note 2 ??? connect to gnd0 to gnd2. ic note 3 ??? connect directly to gnd0 to gnd2. cpureg ??? ? v dd0 ??? ? gnd0 to gnd2 ??? ? adcv dd ??? ? adcgnd ??? ? portv dd ??? ? portgnd ??? ? notes 1. pd703079y, 70f3079y 2. pd70f3079y 3. pd703078y, 703079y
chapter 2 pin functions user?s manual u14665ej2v0um 56 2.5 i/o circuit of pins (1/2) type 2 schmitt-triggered input with hysteresis characteristics type 8 in/out data output disable n-ch p-ch v dd type 4 push-pull output that can be set for high impedance output (both p-ch and n-ch off). type 8-a type 5 type 9 in out output disable n-ch data p-ch v dd pullup enable in/out data output disable n-ch p-ch p-ch v dd v dd output disable input enable in/out data n- ch p-ch v dd + - n- ch p-ch input enable v ref (threshold voltage) comparator in
chapter 2 pin functions user?s manual u14665ej2v0um 57 (2/2) type 10 in/out data open drain output disable n-ch p-ch v dd
user?s manual u14665ej2v0um 58 chapter 3 cpu functions the cpu of the v850/sf1 is based on risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 features ? minimum instruction execution time: 62.5 ns (@ 16 mhz internal operation) ? address space: 16 mb linear ? thirty-two 32-bit general-purpose registers ? internal 32-bit architecture ? five-stage pipeline control ? multiplication/division instructions ? saturated operation instructions ? one-clock 32-bit shift instruction ? load/store instructions with long/short format ? four types of bit manipulation instructions ? set1 ?clr1 ?not1 ?tst1
chapter 3 cpu functions user?s manual u14665ej2v0um 59 3.2 cpu register set the cpu registers in the v850/sf1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers are 32 bits wide. for details, refer to v850 family user?s manual architecture . figure 3-1. cpu register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address register stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) pc program counter psw program status word ecr exception cause register fepc fepsw fatal error pc fatal error psw eipc eipsw exception/interrupt pc exception/interrupt psw 31 0 31 0 31 0 31 0 31 0 31 0 system register set program register set
chapter 3 cpu functions user?s manual u14665ej2v0um 60 3.2.1 program register set the program register set includes general-purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. r2 may be used by the real-time os. r2 can be used as a variable register when the real-time os that is used does not use r2. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os being used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer register to indicate the start of the text area note r6 to r29 address/data variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution note area in which program code is mapped. (2) program counter (pc) this register holds the address of the instruction under execution. the lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. if a carry occurs from bit 23 to 24, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. after reset: 00000000h 31 24 23 1 0 pc fixed to 0 instruction address under execution 0
chapter 3 cpu functions user?s manual u14665ej2v0um 61 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. table 3-2. system register numbers no. system register name usage operation 0eipc 1eipsw interrupt status saving registers these registers save the pc and psw when an exception or interrupt occurs. because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. 2fepc 3fepsw nmi status saving registers these registers save pc and psw when nmi occurs. 4 ecr interrupt source register if exception, maskable interrupt, or nmi occurs, this register will hold information referencing the interrupt source. the higher 16 bits of this register are called fecc, to which the exception code of nmi is set. the lower 16 bits are called eicc, to which the exception code of exception/interrupt is set. 5 psw program status word the program status word is a collection of flags that indicate the program status (instruction execution result) and cpu status. 6 to 31 reserved to read/write these system registers, specify a system register number, indicated by the system register load/store instruction (ldsr or stsr instruction). (1) interrupt source register (ecr) after reset: 00000000h 31 16 15 0 ecr fecc eicc fecc exception code of nmi (for exception code, refer to table 7-1 .) eicc exception code of exception/interrupt
chapter 3 cpu functions user?s manual u14665ej2v0um 62 (2) program status word (psw) bit position bit name function 31 to 8 rfu reserved field (fixed to 0). 7np indicates that non-maskable interrupt (nmi) servicing is in progress. this flag is set when an nmi is acknowledged, and disables multiple interrupts. 0: nmi servicing not under execution. 1: nmi servicing under execution. 6ep indicates that exception processing is in progress. this flag is set when an exception is generated. moreover, interrupt requests can be acknowledged when this bit is set. 0: exception processing not under execution. 1: exception processing under execution. 5id indicates whether a maskable interrupt request can be acknowledged or not. 0: interrupt enabled. 1: interrupt disabled. 4 sat note indicates that the operation result of a saturated operation processing instruction is saturated due to overflow. due to the cumulative flag, if the operation result is saturated by the saturation operation instruction, this bit is set (1), but is not cleared (0) even if the operation results of subsequent instructions are not saturated. to clear (0) this bit, load data in psw. note that in a general arithmetic operation, this bit is neither set (1) nor cleared (0). 0: not saturated. 1: saturated. 3 cy this flag is set if a carry or borrow occurs as the result of an operation (if a carry or borrow does not occur, it is reset). 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note this flag is set if an overflow occurs during operation (if an overflow does not occur, it is reset). 0: overflow does not occur. 1: overflow occurs. 1 s note this flag is set if the result of an operation is negative (it is reset if the result is positive). 0: the operation result was positive or 0. 1: the operation result was negative. 0 z this flag is set if the result of an operation is zero (if the result is not zero, it is reset). 0: the operation result was not 0. 1: the operation result was 0. note the result of a saturation-processed operation is determined by the contents of the ov and s flags in the saturation operation. simply setting the ov flag (1) will set the sat flag (1) in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retains the value before operation 0 1 operation result itself 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz
chapter 3 cpu functions user?s manual u14665ej2v0um 63 3.3 operation modes the v850/sf1 has the following operation modes. (1) normal operation mode (single-chip mode) after the system has been released from the reset status, the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal rom, and instruction processing written in the internal rom is started. however, external expansion mode, in which an external device is connected to external memory area, is enabled by setting in the memory expansion mode register (mm) via an instruction. (2) flash memory programming mode this mode is provided only in the pd70f3079y. the internal flash memory is programmable or erasable when the v pp voltage is applied to the v pp pin. v pp operation mode 0 normal operation mode 7.8 v flash memory programming mode v dd setting prohibited
chapter 3 cpu functions user?s manual u14665ej2v0um 64 3.4 address space 3.4.1 cpu address space the cpu of the v850/sf1 is of 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). when referencing instruction addresses, linear address space (program space) of up to 16 mb is supported. the cpu address space is shown below. figure 3-2. cpu address space ffffffffh cpu address space program area (16 mb linear) data area (4 gb linear) 01000000h 00ffffffh 00000000h
chapter 3 cpu functions user?s manual u14665ej2v0um 65 3.4.2 images a 16 mb physical address space is seen as 256 images in the 4 gb cpu address space. in other words, the same 16 mb physical address space is accessed regardless of the values of bits 31 to 24 of the cpu address. the images of the addressing space are shown below. the physical address xx000000h can be seen as cpu address 00000000h, and in addition, can be seen as addresses 01000000h, 02000000h, ... fe000000h, ff000000h. this is because the higher 8 bits of a 32-bit cpu address are ignored and the cpu address is only accessed as a 24-bit physical address. figure 3-3. images on address space ffffffffh ff000000h feffffffh image cpu address space image image image image fe000000h fdffffffh 02000000h 01ffffffh 01000000h 00ffffffh 00000000h physical address space internal peripheral i/o internal ram (access prohibited) internal rom xxffffffh xx000000h
chapter 3 cpu functions user?s manual u14665ej2v0um 66 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. even if a carry or borrow occurs from bit 23 to 24 as a result of a branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address 00ffffffh are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instruction can be fetched from the 4 kb area of 00fff000h to 00ffffffh because this area is defined as peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. figure 3-4. program space 00fffffeh 00ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. figure 3-5. data space fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ? ) direction
chapter 3 cpu functions user?s manual u14665ej2v0um 67 3.4.4 memory map the v850/sf1 reserves areas as shown below. figure 3-6. memory map xxffffffh internal peripheral i/o area internal ram area fcan address area on-chip flash memory/ rom area internal peripheral i/o area internal ram area fcan address area external memory area on-chip flash memory/ rom area single-chip mode single-chip mode (external expansion mode) 16 mb 1 mb 4 kb xxfff000h xxffefffh xx100000h xx0fffffh xx000000h xxff8000h xxff7fffh 28 kb
chapter 3 cpu functions user?s manual u14665ej2v0um 68 3.4.5 area (1) internal rom/flash memory area a maximum of 1 mb is reserved for the internal rom/flash memory area. 256 kb are available at addresses xx000000h to xx03ffffh. addresses xx040000h to xx0fffffh are an access-prohibited area. figure 3-7. internal rom/flash memory area x x 0 f f f f f h x x 0 4 0 0 0 0 h x x 0 3 f f f f h x x 0 0 0 0 0 0 h access-prohibited area internal rom/ flash memory
chapter 3 cpu functions user?s manual u14665ej2v0um 69 interrupt/exception table the v850/sf1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written at that memory address is executed. the sources of interrupts/exceptions, and the corresponding addresses are shown below. table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00000000h reset 000001b0h inttm4 00000010h nmi 000001c0h inttm5 00000020h intwdt 000001d0h intwtm 00000040h trap0n (n = 0 to f) 000001e0h intwtni 00000050h trap1n (n = 0 to f) 000001f0h intiic0/intcsi0 00000060h ilgop 00000200h intser0 00000080h intwdtm 00000210h intsr0/intcsi1 00000090h intp0 00000220h intst0 000000a0h intp1 00000230h intkr 000000b0h intp2 00000240h intce1 000000c0h intp3 00000250h intcr1 000000d0h intp4 00000260h intct1 000000e0h intp5 00000270h inticme 000000f0h intp6 00000280h inttm6 00000100h intcsi4 00000290h inttm70 00000110h intad 000002a0h inttm71 00000120h intdma0 000002b0h intser1 00000130h intdma1 000002c0h intsr1/intcsi3 00000140h intdma2 000002d0h intst1 00000150h inttm00 000002e0h intdma3 00000160h inttm01 000002f0h intdma4 00000170h inttm10 00000300h intdma5 00000180h inttm11 00000310h intce2 note 00000190h inttm2 00000320h intcr2 note 000001a0h inttm3 00000330h intct2 note note available only for the pd703079y and 70f3079y.
chapter 3 cpu functions user?s manual u14665ej2v0um 70 (2) internal ram area a maximum of 28 kb is reserved for the internal ram area. 16 kb are available at addresses xxffb000h to xxffefffh. addresses xxff8000h to xxffafffh are an access-prohibited area. figure 3-8. internal ram area x x f f e f f f h x x f f b 0 0 0 h x x f f a f f f h x x f f 8 0 0 0 h access-prohibited area internal ram
chapter 3 cpu functions user?s manual u14665ej2v0um 71 (3) internal peripheral i/o area the 4 kb area of addresses fff000h to ffffffh is reserved as an internal peripheral i/o area. in the v850/sf1, the 1 kb area of addresses fff000h to fff3ffh is provided as a physical internal peripheral i/o area, and its image can be seen on the rest of the area (fff400h to ffffffh). peripheral i/o registers associated with functions such as operation mode specification and state monitoring for the internal peripherals are all memory-mapped to the internal peripheral i/o area. program fetches are not allowed in this area. figure 3-9. internal peripheral i/o area xxffffffh xxfffc00h xxfffbffh xxfff800h xxfff7ffh xxfff400h xxfff3ffh xxfff000h image image image physical internal peripheral i/o 3ffh 000h image peripheral i/o cautions 1. the least significant bit of an address is not decoded. if an odd address (2n + 1) in the peripheral i/o area is referenced (accessed in byte units), the register at an even address (2n) will be accessed. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined, if the access is a read operation. if a write access is made, only the data in the lower 8 bits is written to the register. 3. if a register with n address that can be accessed only in halfword units is accessed in word units, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the register with n address and the second operation (higher 16 bits) accesses the register with n + 2 address. 4. if a register with n address that can be accessed in word units is accessed in word units, the operation is replaced with two halfword operations. the first operation (lower 16 bits) accesses the register with n address and the second operation (higher 16 bits) accesses the register with n + 2 address. 5. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed.
chapter 3 cpu functions user?s manual u14665ej2v0um 72 (4) external memory the v850/sf1 can use an area of up to 16 mb (xx100000h to xxff7fffh) for external memory area (in single- chip mode: external expansion). 64 kb, 256 kb, 1 mb, or 4 mb of physical external memory can be allocated when the external expansion mode is specified. in the area of other than the physical external memory, the image of the physical external memory can be seen. the internal ram area and internal peripheral i/o area are not subject to external memory access. caution addresses xxnff800h to xxnfffffh (n = 3, 7, b) constitute an fcan address area and are therefore access-prohibited. figure 3-10. external memory area (when expanded to 64 kb, 256 kb, or 1 mb) xxffffffh xx000000h physical external memory xffffh x0000h internal peripheral i/o internal ram image image image internal rom xxff7fffh xx100000h external memory
chapter 3 cpu functions user?s manual u14665ej2v0um 73 figure 3-11. external memory area (when expanded to 4 mb) xxffffffh xx000000h physical external memory fcan address area external memory 3fffffh 3ff800h 3ff7ffh 000000h internal peripheral i/o internal ram image image xxff7fffh xx100000h xx0fffffh internal rom image xx400000h xx3fffffh xxc00000h xxbfffffh xx800000h xx7fffffh
chapter 3 cpu functions user?s manual u14665ej2v0um 74 3.4.6 external expansion mode the v850/sf1 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. to connect an external device, the port pins must be set to the external expansion mode by using the memory expansion mode register (mm). because the v850/sf1 is fixed to single-chip mode in the normal operation mode, the port alternate-function pins are in the port mode, and therefore the external memory cannot be used. when the external memory is used (external expansion mode), set the mm register by program. (1) memory expansion mode register (mm) this register sets the mode of each pin of ports 4, 5, 6, and 9. in the external expansion mode, an external device can be connected to an external memory area of up to 4 mb. however, the external device cannot be connected to the internal ram area, internal peripheral i/o area, and internal rom area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed). the mm register can be read/written in 8- or 1-bit units. however, bits 4 to 7 are fixed to 0. after reset: 00h r/w address: fffff04ch symbol76543210 mm 0 0 0 0 mm3 mm2 mm1 mm0 mm3 p95 and p96 operation modes 0 port mode 1 external expansion mode (hldak: p95, hldrq: p96) note mm2 mm1 mm0 address space port 4 port 5 port 6 port 9 000 ? port mode 0 1 1 64 kb ad0 to ad8 to lben, expansion mode ad7 ad15 uben, 1 0 0 256 kb a16, r/w, dstb, expansion mode a17 astb 1 0 1 1 mb a18, expansion mode a19 11 4 mb a20, expansion mode a21 other than above rfu (reserved) note before switching to the external expansion mode, be sure to set p95 and p96 of port 9 (p9) to 1. remark for details of the operation of each port pin, refer to 2.3 description of pin functions .
chapter 3 cpu functions user?s manual u14665ej2v0um 75 3.4.7 recommended use of address space the architecture of the v850/sf1 requires that a register that serves as a pointer be secured for address generation in operand data accessing for data space. the address in this pointer register 32 kb can be accessed directly from an instruction. however, the general-purpose registers that can be used as a pointer register are limited. therefore, by minimizing the deterioration of the address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved because instructions for calculating pointer addresses are not required. to enhance the efficiency of using the pointer in connection with the memory maps of the v850/sf1, the following points are recommended: (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. therefore, a continuous 16 mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space for the efficient use of resources that utilize the wraparound feature of the data space, the continuous 8 mb address spaces 00000000h to 007fffffh and ff800000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850/sf1, a 16 mb physical address space is seen as 256 images in the 4 gb cpu address space. the most significant bit (bit 23) of this 24-bit address is assigned as address sign-extended to 32 bits.
chapter 3 cpu functions user?s manual u14665ej2v0um 76 (a) application of wraparound for example, when r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended disp16. all resources including on- chip hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by hardware, and eliminates the need for additional registers for the pointer. figure 3-12. application of wraparound internal rom area internal peripheral i/o area internal ram area 4 kb 16 kb 0007ffffh 00007fffh (r =) 00000000h fffff000h ffffb000h ffff8000h 32 kb 12 kb access-prohibited area
chapter 3 cpu functions user?s manual u14665ej2v0um 77 figure 3-13. recommended memory map (flash memory version) notes 1. this area cannot be used as a program area. 2. addresses xxnf800h to xxnffffh (n = 3, 7, b) are an fcan address area and cannot be accessed during external expansion. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map for the pd70f3079y. ffffffffh fffff400h fffff3ffh 00000000h 16 mb 8 mb internal rom internal rom external memory internal ram internal peripheral i/o note 1 program space data space internal peripheral i/o internal ram external memory internal peripheral i/o internal ram access prohibited area external memory external memory internal rom xxffffffh xxfff400h xxfff3ffh xxfff000h xxffefffh xxffb000h xxffafffh xxff8000h xxff7fffh xx100000h xx0fffffh xx040000h xx03ffffh xx800000h xx7fffffh xx000000h fffff000h ffffefffh ffff8000h ffff7fffh ff800000h ff7fffffh 01000000h 00ffffffh 00fff000h 00ffefffh 00ff8000h 00ff7fffh 00800000h 007fffffh 00100000h 000fffffh 00040000h 0003ffffh note 2
chapter 3 cpu functions user?s manual u14665ej2v0um 78 3.4.8 peripheral i/o registers (1/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff000h port 0 p0 ? fffff002h port 1 p1 ? fffff004h port 2 p2 ? fffff006h port 3 p3 ? fffff008h port 4 p4 ? fffff00ah port 5 p5 ? fffff00ch port 6 p6 r/w ? 00h note fffff00eh port 7 p7 ? fffff010h port 8 p8 r ? undefined fffff012h port 9 p9 ? fffff014h port 10 p10 ? fffff016h port 11 p11 ? 00h note fffff020h port 0 mode register pm0 ? ffh fffff022h port 1 mode register pm1 ? 3fh fffff024h port 2 mode register pm2 ? fffff026h port 3 mode register pm3 ? fffff028h port 4 mode register pm4 ? fffff02ah port 5 mode register pm5 ? ffh fffff02ch port 6 mode register pm6 ? 3fh fffff032h port 9 mode register pm9 ? 7fh fffff034h port 10 mode register pm10 ? ffh fffff036h port 11 mode register pm11 ? ffh fffff040h port alternate function control register pac ? fffff04ch memory expansion mode register mm ? 00h fffff060h data wait control register dwc ffffh fffff062h bus cycle control register bcc aaaah fffff070h power save control register psc ? c0h fffff074h processor clock control register pcc ? 03h fffff078h system status register sys r/w ? 00h note resetting initializes registers to input mode, so 00h cannot actually be read.
chapter 3 cpu functions user?s manual u14665ej2v0um 79 (2/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff07ah poc status register pocs r held note 1 fffff07ch vm45 control register vm45c fffff094h pull-up resistor option register 10 pu10 ? fffff0a2h port 1 function register pf1 ? fffff0c0h rising edge specification register 0 egp0 ? fffff0c2h falling edge specification register 0 egn0 ? fffff0e4h timer clock selection register 30 tcl30 00h fffff0e6h timer mode control register 30 tmc30 r/w ? 04h note 2 fffff0eah 16-bit counter 3 tm3 r fffff0ech 16-bit compare register 3 cr3 0000h fffff0eeh timer clock selection register 31 tlc31 00h fffff100h interrupt control register wdtic ? fffff102h interrupt control register pic0 ? fffff104h interrupt control register pic1 ? fffff106h interrupt control register pic2 ? fffff108h interrupt control register pic3 ? fffff10ah interrupt control register pic4 ? fffff10ch interrupt control register pic5 ? fffff10eh interrupt control register pic6 ? fffff110h interrupt control register csic4 ? fffff112h interrupt control register adic ? fffff114h interrupt control register dmaic0 ? fffff116h interrupt control register dmaic1 ? fffff118h interrupt control register dmaic2 ? fffff11ah interrupt control register tmic00 ? fffff11ch interrupt control register tmic01 ? fffff11eh interrupt control register tmic10 ? fffff120h interrupt control register tmic11 ? fffff122h interrupt control register tmic2 ? fffff124h interrupt control register tmic3 ? fffff126h interrupt control register tmic4 ? fffff128h interrupt control register tmic5 ? fffff12ah interrupt control register wtnic ? fffff12ch interrupt control register wtniic ? fffff12eh interrupt control register csic0 r/w ? 47h notes 1. this value is 03h only after a power-on-clear reset. this cannot be reset by reset signal input or watchdog timer. 2. although the hardware status is initialized to 04h, 00h is read out if read.
chapter 3 cpu functions user?s manual u14665ej2v0um 80 (3/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff130h interrupt control register seric0 ? fffff132h interrupt control register csic1 ? fffff134h interrupt control register stic0 ? fffff136h interrupt control register kric ? fffff138h interrupt control register canic1 ? fffff13ah interrupt control register canic2 ? fffff13ch interrupt control register canic3 ? fffff13eh interrupt control register canic7 ? fffff140h interrupt control register tmic6 ? fffff142h interrupt control register tmic70 ? fffff144h interrupt control register tmic71 ? fffff146h interrupt control register seric1 ? fffff148h interrupt control register csic3 ? fffff14ah interrupt control register stic1 ? fffff14ch interrupt control register dmaic3 ? fffff14eh interrupt control register dmaic4 ? fffff150h interrupt control register dmaic5 ? fffff152h interrupt control register note canic4 ? fffff154h interrupt control register note canic5 ? fffff156h interrupt control register note canic6 r/w ? 47h fffff166h in-service priority register ispr r ? 00h fffff170h command register prcmd w fffff180h dma peripheral i/o address register 0 dioa0 fffff182h dma internal ram address register 0 dra0 fffff184h dma byte count register 0 dbc0 undefined fffff186h dma channel control register 0 dchc0 ? 00h fffff190h dma peripheral i/o address register 1 dioa1 fffff192h dma internal ram address register 1 dra1 fffff194h dma byte count register 1 dbc1 undefined fffff196h dma channel control register 1 dchc1 ? 00h fffff1a0h dma peripheral i/o address register 2 dioa2 fffff1a2h dma internal ram address register 2 dra2 fffff1a4h dma byte count register 2 dbc2 undefined fffff1a6h dma channel control register 2 dchc2 ? 00h fffff1b0h dma peripheral i/o address register 3 dioa3 fffff1b2h dma internal ram address register 3 dra3 r/w undefined note available only for the pd703079y and 70f3079y.
chapter 3 cpu functions user?s manual u14665ej2v0um 81 (4/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff1b4h dma byte count register 3 dbc3 undefined fffff1b6h dma channel control register 3 dchc3 ? 00h fffff1c0h dma peripheral i/o address register 4 dioa4 fffff1c2h dma internal ram address register 4 dra4 fffff1c4h dma byte count register 4 dbc4 undefined fffff1c6h dma channel control register 4 dchc4 ? 00h fffff1d0h dma peripheral i/o address register 5 dioa5 fffff1d2h dma internal ram address register 5 dra5 fffff1d4h dma byte count register 5 dbc5 undefined fffff1d6h dma channel control register 5 dchc5 r/w ? 00h fffff200h 16-bit timer register 0 tm0 r fffff202h 16-bit capture/compare register 00 cr00 note fffff204h 16-bit capture/compare register 01 cr01 note 0000h fffff206h prescaler mode register 00 prm00 fffff208h 16-bit timer mode control register 0 tmc0 ? fffff20ah capture/compare control register 0 crc0 ? fffff20ch timer output control register 0 toc0 ? fffff20eh prescaler mode register 01 prm01 r/w 00h fffff210h 16-bit timer register 1 tm1 r fffff212h 16-bit capture/compare register 10 cr10 note fffff214h 16-bit capture/compare register 11 cr11 note 0000h fffff216h prescaler mode register 10 prm10 fffff218h 16-bit timer mode control register 1 tmc1 ? fffff21ah capture/compare control register 1 crc1 ? fffff21ch timer output control register 1 toc1 ? fffff21eh prescaler mode register 11 prm11 fffff244h timer clock select register 20 tcl20 00h fffff246h timer mode control register 20 tmc2 r/w ? 04h fffff24ah 16-bit counter 2 tm2 r fffff24ch 16-bit compare register 2 cr2 0000h fffff24eh timer clock selection register 21 tcl21 r/w 00h note in compare mode: r/w in capture mode: r
chapter 3 cpu functions user?s manual u14665ej2v0um 82 (5/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff264h timer clock selection register 40 tcl40 r/w 00h fffff266h timer mode control register 40 tmc40 ? 04h note fffff26ah 16-bit counter 4 tm4 r 0000h fffff26ch 16-bit compare register 4 cr4 fffff26eh timer clock selection register 41 tcl41 fffff284h timer clock selection register 60 tcl60 00h fffff286h timer mode control register 60 tmc60 r/w ? 04h note fffff28ah 16-bit counter 6 tm6 r fffff28ch 16-bit compare register 6 cr6 0000h fffff28eh timer clock selection register 61 tcl61 fffff2a0h serial i/o shift register 0 sio0 fffff2a2h serial operation mode register 0 csim0 ? fffff2a4h serial clock selection register 0 csis0 fffff2b0h serial i/o shift register 1 sio1 fffff2b2h serial operation mode register 1 csim1 ? fffff2b4h serial clock selection register 1 csis1 fffff2d0h serial i/o shift register 3 sio3 fffff2d2h serial operation mode register 3 csim3 ? fffff2d4h serial clock selection register 3 csis3 00h fffff2e0h variable-length serial i/o shift register 4 sio4 0000h fffff2e2h variable-length serial control register 4 csim4 ? fffff2e4h variable-length serial setting register 4 csib4 ? fffff2e6h baud rate generator source clock selection register 4 brgcn4 00h fffff2e8h baud rate generator output clock selection register 4 brgck4 7fh fffff300h asynchronous serial interface mode register 0 asim0 r/w ? fffff302h asynchronous serial interface status register 0 asis0 r ? fffff304h baud rate generator control register 0 brgc0 r/w 00h fffff306h transmission shift register 0 txs0 w fffff308h reception buffer register 0 rxb0 r ffh fffff30eh baud rate generator mode control register 00 brgmc00 fffff310h asynchronous serial interface mode register 1 asim1 r/w ? fffff312h asynchronous serial interface status register 1 asis1 r ? fffff314h baud rate generator control register 1 brgc1 r/w 00h fffff316h transmission shift register 1 txs1 w fffff318h reception buffer register 1 rxb1 r ffh note although the hardware status is initialized to 04h, 00h is read out if read.
chapter 3 cpu functions user?s manual u14665ej2v0um 83 (6/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff31eh baud rate generator mode control register 10 brgmc10 fffff320h baud rate generator mode control register 01 brgmc01 fffff322h baud rate generator mode control register 11 brgmc11 fffff334h timer clock selection register 50 tcl50 fffff336h timer mode control register 50 tmc50 r/w ? 00h fffff33ah 16-bit counter 5 tm5 r fffff33ch 16-bit compare register 5 cr5 0000h fffff33eh timer clock selection register 51 tcl51 fffff340h iic control register 0 iicc0 r/w ? fffff342h iic state register 0 iics0 r ? fffff344h iic clock selection register 0 iiccl0 ? fffff346h slave address register 0 sva0 fffff348h iic shift register 0 iic0 fffff34ah iic function expansion register 0 iicx0 ? fffff34ch iic clock expansion register 0 iicce0 fffff360h watch timer mode register wtnm ? fffff364h watch timer clock selection register wtncs fffff36ch correction control register corcn ? fffff36eh correction request register corrq ? 00h fffff370h correction address register 0 corad0 fffff374h correction address register 1 corad1 fffff378h correction address register 2 corad2 fffff37ch correction address register 3 corad3 00000000h fffff380h oscillation stabilization time selection register osts 04h fffff382h watchdog timer clock selection register wdcs fffff384h watchdog timer mode register wdtm ? fffff38eh dma start factor expansion register dmas ? 00h fffff3a0h 16-bit timer register 7 tm7 fffff3a2h 16-bit capture/compare register 70 cr70 fffff3a4h 16-bit capture/compare register 71 cr71 0000h fffff3a6h prescaler mode register 70 prm70 fffff3a8h 16-bit timer mode control register 7 tmc7 ? fffff3aah capture/compare control register 7 crc7 ? fffff3ach timer output control register 7 toc7 ? fffff3aeh prescaler mode register 71 prm71 fffff3c0h a/d converter mode register 1 adm1 ? fffff3c2h analog input channel specification register ads r/w ? 00h
chapter 3 cpu functions user?s manual u14665ej2v0um 84 (7/7) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits 32 bits after reset fffff3c4h a/d conversion result register adcr 0000h fffff3c6h a/d conversion result register h (higher 8 bits) adcrh r fffff3c8h a/d converter mode register 2 adm2 ? fffff3d0h key return mode register krm ? fffff3d4h noise elimination control register ncc r/w 00h
chapter 3 cpu functions user?s manual u14665ej2v0um 85 3.4.9 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the write access of these specific registers is executed in a specific sequence, and the occurrence of abnormal store operations is reported by the system status register (sys). the v850/sf1 has two specific registers, the power save control register (psc) and processor clock control register (pcc). for details of the psc register, refer to 4.3.1 (2) power save control register (psc), and for details of the pcc register, refer to 4.3.1 (1) processor clock control register (pcc). the following sequence shows the data setting of the specific registers. <1> disable dma operation. <2> disable interrupts (set the psw np bit to 1). <3> write any 8-bit data in the command register (prcmd). <4> write the data to be set in the specific registers (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> cancel the interrupt-disabled state (return the psw np bit to 0). <6> insert nop instructions (2 or 5 instructions). <7> if necessary, enable dma operation. no special sequence is required when reading the specific registers. cautions 1. if an interrupt request or a dma request is acknowledged between the time prcmd is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (prerr bit of sys register is 1) may occur. therefore, set the np bit of psw to 1 (<2>) to disable the acknowledgement of int/nmi or to disable dma transfer. the above also applies when a bit manipulation instruction is used to set a specific register. moreover, to ensure that the execution routine following release of the stop/idle mode is performed correctly, insert a nop instruction as a dummy instruction (<6>). if the value of the id bit of the psw does not change as the result of execution of the instruction to return the np bit to 0 (<5>), insert two nop instructions, and if the value of the id bit of the psw changes, insert five nop instructions.
chapter 3 cpu functions user?s manual u14665ej2v0um 86 a description example is given below. [description example]: in case of psc register ldsr rx,5 ; np bit = 1 st.b r0,prcmd [r0] ; write to prcmd st.b rd,psc [r0] ; psc register setting ldsr ry,5 ; np bit = 0 nop ; dummy instruction (2 or 5 instructions) . . . nop (next instruction) ; execution routine following cancellation of stop/idle mode . . . rx: value to be written to psw ry: value to be written back to psw rd: value to be set to psc when saving the value of the psw, the value of the psw prior to setting the np bit must be transferred to the ry register. cautions 2. the instructions (<5> interrupt disable cancel, <6> nop instruction) following the store instruction for the psc register for setting the software stop mode and idle mode are executed before a power save mode is entered. 3. always stop dma prior to accessing specific registers.
chapter 3 cpu functions user?s manual u14665ej2v0um 87 (1) command register (prcmd) the command register (prcmd) is used to prevent incorrect writing to the specific registers due to an inadvertent program loop when write-accessing the specific register. this register can be written in 8-bit units. it becomes undefined in a read cycle. the occurrence of illegal store operations can be checked by the prerr bit of the sys register. after reset: undefined w address: fffff170h 76543210 prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 regn registration code 0/1 any 8-bit data (2) system status register (sys) this register is allocated with status flags showing the operating state of the entire system. this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff078h 76543210 sys 0 0 0 prerr 0 0 0 0 prerr detection of protection error 0 protection error did not occur 1 protection error occurred the operation conditions of prerr flag are shown below. (a) set conditions (prerr = 1) (1) when a write operation to a specific register took place in a state where the store instruction operation for the recent peripheral i/o was not a write operation to the prcmd register. (2) when the first store instruction operation following a write operation to the prcmd register is to any peripheral i/o register apart from specific registers. (b) reset conditions: (prerr = 0) (1) when 0 is written to the prerr flag of the sys register. (2) at system reset.
88 user?s manual u14665ej2v0um chapter 4 clock generation function 4.1 general the clock generator is a circuit that generates the clock pulses that are supplied to the cpu and peripheral hardware. there are two types of system clock oscillators. (1) main system clock oscillator the oscillator of v850/sf1 has an oscillation frequency of 2 to 16 mhz. oscillation can be stopped by executing a stop instruction or by setting the processor clock control register (pcc). oscillation is also stopped during a reset. in idle mode, supplying the peripheral clock to the clock timer only is possible. therefore, in idle mode, it is possible to operate the clock timer without using the subsystem clock oscillator. cautions 1. when the main oscillator is stopped by inputting a reset or executing a stop instruction, oscillation stabilization time is secured after the stop mode is canceled. this oscillation stabilization time is set via the oscillation stabilization time selection register (osts). the watchdog timer is used to count the oscillation stabilization time. 2. if the main system clock halt is released by clearing the mck bit to 0 after the main system clock is stopped by setting the mck bit in the pcc register to 1, the oscillation stabilization time is not secured. 3. external clock input is disabled. (2) subsystem clock oscillator this circuit has an oscillation frequency of 32.768 khz. its oscillation is not stopped when the stop instruction is executed, nor when a reset is input. when the subsystem clock oscillator is not used, the frc bit in the processor clock control register (pcc) can be set to disable use of the internal feedback resistor. this enables the current consumption to be kept low in the stop mode. 4.2 configuration figure 4-1. clock generator f xt f xt f xx /8 f xx stop, mck frc prescaler prescaler x2 x1 xt2 xt1 idle main system clock oscillator subsystem clock oscillator idle control idle control selector clock supplied to watch timer, etc. clock supplied to peripheral hardware halt halt control cpu clock (f cpu ) clkout f xx /4 f xx /2
chapter 4 clock generation function user?s manual u14665ej2v0um 89 4.3 clock output function this function outputs the cpu clock via the clkout pin. when clock output is enabled, the cpu clock is output via the clkout pin. when it is disabled, a low-level signal is output via the clkout pin. output is stopped in the idle or stop mode (fixed to low level). this function is controlled via the dclk1 and dclk0 bits in the psc register. a high-impedance status is set during the reset period. after reset is canceled, a low level is output. caution while clkout is being output, the cpu clock (ck2 to ck0 bits of pcc register) cannot be changed. 4.3.1 control registers (1) processor clock control register (pcc) this is a specific register. it can be written to only when a specified combination of sequences is used (see 3.4.9 specific registers ). this register can be read/written in 8- or 1-bit units. after reset: 03h r/w address: fffff074h 76543210 pcc frc mck 0 0 0 ck2 ck1 ck0 frc selection of internal feedback resistor for subsystem clock 0used 1 not used mck operation of main system clock 0 operating 1 stopped ck2 note ck1 ck0 selection of cpu clock 000f xx 001f xx /2 010f xx /4 011f xx /8 1xxf xt (subsystem clock)
chapter 4 clock generation function user?s manual u14665ej2v0um 90 note it is recommended to manipulate ck2 in 1-bit units. however, when manipulating the pcc register in 8-bit units, be sure not to change the values of ck1 and ck0. cautions 1. do not change the cpu clock (the value of the ck2 to ck0 in the pcc register) while clkout is being output. 2. even if the mck bit is set to 1 during main clock operation, the main clock is not stopped. the cpu clock stops after the subsystem clock is selected. remark x: either 0 or 1 (a) example of main clock operation subsystem clock operation setup <1> ck2 1: bit manipulation instructions are recommended. do not change ck1 and ck0. <2> subsystem clock operation: the maximum number of the following instructions is required before subsystem clock operation after the ck2 bit is set. (cpu clock frequency before setting / subsystem clock frequency) 2 therefore, insert waits equivalent to this number by program. <3> mck 1: only when the main clock is stopped. (b) example of subsystem clock operation main clock operation setup <1> mck 0: main clock oscillation start <2> insert waits by program and wait until the main clock oscillation stabilization time elapses. <3> ck2, ck1, ch0 cpu clock <4> main clock operation: if ck1 and ck0 are not changed from the cpu clock selection values set before the subsystem clock operation, a maximum of two instructions is required. if ck1 and ck0 are changed, a maximum of ten instructions is required.
chapter 4 clock generation function user?s manual u14665ej2v0um 91 (2) power save control register (psc) this is a specific register. it can be written to only when a specified combination of sequences is used. for details, see 3.4.9 specific registers . this register can be read/written in 8- or 1-bit units. after reset: c0h r/w address: fffff070h 76543210 psc dclk1 dclk0 0 0 0 idle stp 0 dclk1 dclk0 specification of clkout pin operation 00 output enabled 01 setting prohibited 10 setting prohibited 11 output disabled (when reset) idle idle mode setting 0 normal mode 1 idle mode note 1 stp stop mode setting 0 normal mode 1 stop mode note 2 notes 1. when idle mode is canceled, this bit is automatically reset to 0. 2. when stop mode is canceled, this bit is automatically reset to 0. caution the bits in dclk0 and dclk1 should be manipulated in 8-bit units.
chapter 4 clock generation function user?s manual u14665ej2v0um 92 (3) oscillation stabilization time selection register (osts) this register can be read/written in 8-bit units. after reset: 04h r/w address: fffff380h 76543210 osts 0 0 0 0 0 osts2 osts1 osts0 selection of oscillation stabilization time f xx osts2 osts1 osts0 clock 16 mhz 8 mhz 0002 16 /f xx 4.10 ms 8.19 ms 0012 18 /f xx 16.4 ms 32.8 ms 0102 19 /f xx 32.8 ms 65.5 ms 0112 20 /f xx 65.5 ms 131 ms 1002 21 /f xx 131 ms 262 ms other than above setting prohibited
chapter 4 clock generation function user?s manual u14665ej2v0um 93 4.4 power save functions 4.4.1 general this product provides the following power saving functions. these modes can be combined and switched to suit the target application, thus enabling the effective implementation of low-power systems. (1) halt mode in this mode, the clock oscillator continues to operate but the cpu operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. this enables the system?s total power consumption to be reduced. a special-purpose instruction (the halt instruction) is used to switch to halt mode. (2) idle mode this mode stops the entire system by stopping the cpu operating clock as well as the operating clock for on-chip peripheral functions while the clock oscillator is still operating. however, the subsystem clock continues to operate and supplies a clock to the on-chip peripheral functions. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when the idle bit in the power saving control register (psc) is set (1), the system switches to idle mode. (3) software stop mode this mode stops the entire system by stopping the clock oscillator for the main clock. the subsystem clock continues to be supplied to keep on-chip peripheral functions operating. if the subsystem clock is not used, ultra- low-power-consumption mode (leak current only) is set. stop mode setting is prohibited if the cpu is operating via the subsystem clock. if the stp bit of the psc register is set (1), the system enters stop mode. (4) subsystem clock operation in this mode, the cpu clock is set to operate using the subsystem clock and the mck bit of the pcc register is set (1) to set low-power-consumption mode in which the entire system operates using only the subsystem clock. when halt mode has been set, the cpu operating clock is stopped so that power consumption can be reduced. when idle mode has been set, the cpu operating clock and some peripheral functions (dmac and bcu) are stopped to enable an even greater reduction in power consumption than when in halt mode.
chapter 4 clock generation function user?s manual u14665ej2v0um 94 4.4.2 halt mode (1) settings and operating states in this mode, the clock oscillator continues to operate but the cpu operating clock is stopped. a clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. when halt mode is set while the cpu is idle, it enables the system?s total power consumption to be reduced. when in halt mode, execution of programs is stopped but the contents of all registers and on-chip ram are retained as they were just before halt mode was set. in addition, all on-chip peripheral functions that do not depend on instruction processing by the cpu continue operating. halt mode can be set by executing the halt instruction. it can be set when the cpu is operating via either the main clock or subsystem clock. the operating statuses in the halt mode are listed in table 4-1. (2) cancellation of halt mode halt mode can be canceled by an nmi request, an unmasked maskable interrupt request, or reset input. (a) cancellation by interrupt request halt mode is canceled regardless of the priority level when an nmi request or an unmasked maskable interrupt request occurs. however, the following occurs if halt mode was set as part of an interrupt servicing routine. (i) when an interrupt request that has a lower priority level than the interrupt currently being serviced occurs, only halt mode is canceled and the lower-priority interrupt request is not acknowledged. the interrupt request itself is retained. (ii) when an interrupt request (including nmi request) that has a higher priority level than the interrupt currently being serviced occurs, halt mode is canceled and the interrupt request is acknowledged. (b) cancellation by reset pin input this is the same as for normal reset operations.
chapter 4 clock generation function user?s manual u14665ej2v0um 95 table 4-1. operating statuses in halt mode (1/2) halt mode setting when cpu operates on main clock when cpu operates on subsystem clock item when subsystem clock does not exist when subsystem clock exists when main clock oscillation continues when main clock oscillation is stopped cpu stopped rom correction stopped clock generator oscillation for main clock and subsystem clock clock supply to cpu is stopped 16-bit timer (tm0) operating operates when intwti is selected as count clock (f xt is selected for watch timer) 16-bit timer (tm1) operating stopped 16-bit timer (tm2) operating stopped 16-bit timer (tm3) operating stopped 16-bit timer (tm4) operates when other than f xt is selected for count clock operating operates when f xt is selected for count clock 16-bit timer (tm5) operates when other than f xt is selected for count clock operating operates when f xt is selected for count clock 16-bit timer (tm6) operating stopped 16-bit timer (tm7) operating stopped watch timer operates when main clock is selected for count clock operating operates when f xt is selected for count clock watchdog timer operating (interval timer only) csi0 , csi1, csi3 operating operates when an external clock is selected as the serial clock i 2 c0 operating stopped serial interface uart0, uart1 operating operates when an external clock is selected as the baud rate clock csi4 operating operates when an external clock is selected as the serial clock fcan1, fcan2 note operating stopped a/d converter operating stopped dma0 to dma5 operating note available only for the pd703079y, 70f3079y.
chapter 4 clock generation function user?s manual u14665ej2v0um 96 table 4-1. operating statuses in halt mode (2/2) halt mode setting when cpu operates on main clock when cpu operates on subsystem clock item when subsystem clock does not exist when subsystem clock exists when main clock oscillation continues when main clock oscillation is stopped port function held external bus interface only bus hold function operates nmi operating intp0 to intp3 operating intp4 and intp5 operating st opped external interrupt request intp6 operates when other than f xt is selected for noise eliminator operating operates when f xt is selected for noise eliminator key return function operating ad0 to ad15 high impedance note a16 to a21 lben, uben held note (high impedance when hldak = 0) r/w high level output note (high impedance when hldak = 0) dstb astb in external expansion mode hldak operating note even when the halt instruction has been executed, the instruction fetch operation continues until the on-chip instruction prefetch queue becomes full. once it is full, operation stops in the state shown in table 4-1.
chapter 4 clock generation function user?s manual u14665ej2v0um 97 4.4.3 idle mode (1) settings and operating states this mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. supply to the subsystem clock continues. when this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. when in idle mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before idle mode was set. in addition, on-chip peripheral functions are stopped (except for peripheral functions that are operating with the subsystem clock). external bus hold requests (hldrq) are not acknowledged. when the idle bit of the power save control register (psc) is set (1), the system switches to idle mode. the operating statuses in idle mode are listed in table 4-2. (2) cancellation of idle mode idle mode can be canceled by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral i/o, or reset input. table 4-2. operating statuses in idle mode (1/2) idle mode settings w hen subsystem clock exists when subsystem clock does not exist cpu stopped rom correction stopped clock generator both a main clock and subsystem clock oscillator clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected as count clock (f xt is selected for watch timer) stopped 16-bit timer (tm1) stopped 16-bit timer (tm2) stopped 16-bit timer (tm3) stopped 16-bit timer (tm4) operates when f xt is selected for count clock stopped 16-bit timer (tm5) operates when f xt is selected for count clock stopped 16-bit timer (tm6) stopped 16-bit timer (tm7) stopped watch timer operating watchdog timer stopped csi0, csi1, csi3 operates when an external clock is selected as the serial clock i 2 c0 stopped uart0, uart1 operates when an external clock is selected as the baud rate clock serial interface csi4 operates when an external clock is selected as the serial clock fcan1, fcan2 note stopped a/d converter stopped dma0 to dma5 stopped port function held note available only for the pd703079y, 70f3079y. item
chapter 4 clock generation function user?s manual u14665ej2v0um 98 table 4-2. operating statuses in idle mode (2/2) idle mode settings when subsystem clock exists when subsystem clock does not exist external bus interface stopped nmi operating intp0 to intp3 operating intp4 and intp5 stopped external interrupt request intp6 operates when f xt is selected for sampling clock stopped key return function operating ad0 to ad15 a16 to a21 lben, uben r/w dstb astb in external expansion mode hldak high impedance item
chapter 4 clock generation function user?s manual u14665ej2v0um 99 4.4.4 software stop mode (1) settings and operating states this mode stops the entire system by stopping the main clock oscillator supplying the internal main clock. the subsystem clock oscillator continues operating and the internal subsystem clock supply is continued. if the frc bit in the processor clock control register (pcc) is set (1) when the subsystem clock oscillator is used, the subsystem clock oscillator?s on-chip feedback resistor is cut. this sets ultra-low-power-consumption mode, in which the only current is the device?s leak current. in this mode, program execution is stopped and the contents of all registers and internal ram are retained as they were just before software stop mode was set. this mode can be set only when the main clock is being used as the cpu clock. this mode is set when the stp bit in the power save control register (psc) has been set to 1. do not set this mode when the subsystem clock has been selected as the cpu clock. the operating statuses for software stop mode are listed in table 4-3. caution in order to reduce the current consumption in software stop mode, be sure to initialize the fcan settings as described below, regardless of the use of fcan. <1> set the gom bit of the cgst register to ?1? (set gom = 1, clear gom = 0) <2> set the smno1 and smno0 bits of the cgmss register to ?01? <3> set the gom bit of the cgst register to ?0? (set gom = 0, clear gom = 1) for details of fcan settings, refer to chapter 18 fcan controller. (2) cancellation of software stop mode software stop mode can be canceled by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral i/o, or reset input. when the stop mode is canceled, oscillation stabilization time must be secured.
chapter 4 clock generation function user?s manual u14665ej2v0um 100 table 4-3. operating statuses in software stop mode stop mode settings item when subsystem clock exists when subsystem clock does not exist cpu stopped rom correction stopped clock generator oscillation for main clock is stopped and oscillation for subsystem clock continues clock supply to cpu and on-chip peripheral functions is stopped 16-bit timer (tm0) operates when intwtni is selected for count clock (f xt is selected as count clock for watch timer) stopped 16-bit timer (tm1) stopped 16-bit timer (tm2) stopped 16-bit timer (tm3) stopped 16-bit timer (tm4) operates when f xt is selected for count clock stopped 16-bit timer (tm5) operates when f xt is selected for count clock stopped 16-bit timer (tm6) stopped 16-bit timer (tm7) stopped watch timer operates when f xt is selected for count clock stopped (operation disabled) watchdog timer stopped csi0, csi1, csi3 operates when an external clock is selected as the serial clock i 2 c0 stopped uart0, uart1 operates when an external clock is selected as the baud rate clock serial interface csi4 operates when an external clock is selected as the serial clock fcan1, fcan2 note stopped a/d converter stopped dma0 to dma5 stopped port function held external bus interface stopped nmi operating intp0 to intp3 operating intp4 and intp5 stopped external interrupt request intp6 operates when f xt is selected for the sampling clock stopped key return function operating ad0 to ad15 a16 to a21 lben, uben r/w dstb astb in external expansion mode hldak high impedance note available only for the pd703079y and 70f3079y.
chapter 4 clock generation function user?s manual u14665ej2v0um 101 4.5 oscillation stabilization time the following shows methods for specifying the length of oscillation stabilization time required to stabilize the oscillator following cancelation of stop mode. (1) cancelation by non-maskable interrupt or by unmasked maskable interrupt request stop mode is canceled by a non-maskable interrupt or an unmasked maskable interrupt request. when an interrupt is input, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse until the oscillator?s clock output stabilizes. oscillation stabilization time = ? ? wdt count time after the specified amount of time has elapsed, system clock output starts and processing branches to the interrupt handler address. figure 4-2. oscillation stabilization time stop mode is set oscillator is stopped interrupt input oscillation wave main clock stop status count time value of time base counter (2) use of reset pin to allocate time (reset pin input) for allocating time with the reset pin, refer to chapter 14 reset function .
chapter 4 clock generation function user?s manual u14665ej2v0um 102 4.6 cautions on power save function if the v850/sf1 is used under the following conditions, a discrepancy occurs between the address indicated by the program counter (pc) and the address at which an instruction is actually read after the power save mode is released. this may result in the cpu ignoring a 4- or 8-byte instruction from between 4 bytes and 16 bytes after an instruction is executed to write to the psc register, which could in turn result in the execution of an erroneous instruction. [conditions] (i) setting of power save mode (idle mode or stop mode) while an instruction is being executed on external rom (ii) cancelation of power save mode as the result of an interrupt request (iii) execution of the next instruction when an interrupt request is held pending following cancelation of the power save mode conditions for interrupt request to be held pending: ? when np flag of psw register is ?1? (nmi servicing in progress/set by software) ? when id flag of psw register is ?1? (interrupt request servicing in progress/di instruction/set by software) ? when an interrupt enable (ei) state occurs during interrupt request servicing, but this state is cleared by an interrupt request with the same or lower priority therefore, use the v850/sf1 under the following conditions. [usage conditions] (i) do not use a power save mode (idle mode or stop mode) during instruction execution on external rom. (ii) if it is necessary to use a power save mode during instruction execution on external rom, implement the following software measures. ? insert 6 nop instructions 4 bytes after an instruction that writes to the psc register. ? after the nop instructions, insert a br$+2 instruction to cancel the pc discrepancy.
chapter 4 clock generation function user?s manual u14665ej2v0um 103 [workaround program example] ldsr rx,5 ; sets rx value to psw st.b r0,prcmd[r0] ; writes to prcmd st.b rd,psc[r0] ; sets psc register ldsr ry,5 ; returns psw value nop ;6 or more nop instructions nop nop nop nop nop br $+2 ; cancels pc discrepancy remark it is assumed that rd (psc setting value), rx (value written to psw), and ry (value written back to psw) have been set.
user?s manual u14665ej2v0um 104 chapter 5 port function 5.1 port configuration the v850/sf1 includes 84 port pins from ports 0 to 11, of which 72 are i/o pins and 12 are input only pins. there are two pin i/o buffer power supplies: adcv dd and portv dd , which are described below. table 5-1. pin i/o buffer power supplies power supply corresponding pins adcv dd port 7, port 8 portv dd port 0, port 1, port 2, port 3, port 4, port 5, port 6, port 9, port 10, port 11, reset, clkout 5.2 port pin functions 5.2.1 port 0 port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. when using p00 to p04 as the nmi or intp0 to intp3 pins, noise is eliminated by an analog noise eliminator. when using p05 to p07 as the intp4/adtrg, intp5, and intp6 pins, noise is eliminated by a digital noise eliminator. after reset: 00h r/w address: fffff000h 76543210 p0 p07 p06 p05 p04 p03 p02 p01 p00 p0n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when the p0 register is read, the pin levels at that time are read. writing to p0 writes the values to that register. this does not affect the input pins. in output mode: when the p0 register is read, the values of p0 are read. writing to p0 writes the values to that register, and those values are immediately output.
chapter 5 port function user?s manual u14665ej2v0um 105 port 0 includes the following alternate functions. table 5-2. port 0 alternate function pins pin name alternate function i/o pull note remark p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 analog noise elimination p05 intp4/adtrg p06 intp5 port 0 p07 intp6 i/o no digital noise elimination note software pull-up function (1) function of p0 pins port 0 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 0 mode register (pm0). in output mode, the values set to each bit are output to port 0 (p0). when using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for nmi requests). when using this port in input mode, the pin statuses can be read by reading p0. also, the values of p0 (output latch) can be read by reading p0 while in output mode. the valid edges of nmi and intp0 to intp6 are specified via rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0). when a reset is input, the settings are initialized to input mode. also, the valid edge of each interrupt request becomes invalid (nmi and intp0 to intp6 do not function immediately after reset). (2) noise elimination (a) elimination of noise from nmi and intp0 to intp3 pins an on-chip noise eliminator is provided that uses analog delay to eliminate noise. consequently, if a signal having a constant level is input for longer than a specified time to these pins, it is detected as a valid edge. such edge detection occurs only after the specified amount of time. (b) elimination of noise from intp4 to intp6 and adtrg pins a digital noise eliminator is provided on chip. this circuit uses digital sampling. a pin?s input level is detected using a sampling clock (f xx ), and noise elimination is performed for the intp4, intp5, and adtrg pins if the same level is not detected three times consecutively. the noise-elimination width can be changed for the intp6 pin (see 7.3.8 (3) noise elimination of intp6 pin ).
chapter 5 port function user?s manual u14665ej2v0um 106 cautions 1. if the input pulse width is 2 or 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undefined. to ensure correct detection of the valid edge, constant-level input is required for 3 clocks or more. 2. if noise is occurring in synchronization with the sampling clock, it may not be recognized as noise. in such cases, attach a filter to the input pins to eliminate the noise. 3. noise elimination is not performed when these pins are used as an ordinary input port. (3) control registers (a) port 0 mode register (pm0) pm0 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff020h 76543210 pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) rising edge specification register 0 (egp0) egp0 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c0h 76543210 egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n control of rising edge detection (n = 0 to 7) 0 interrupt request signal did not occur at rising edge 1 interrupt request signal occurred at rising edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins
chapter 5 port function user?s manual u14665ej2v0um 107 (c) falling edge specification register 0 (egn0) egn0 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0c2h 76543210 egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n control of falling edge detection (n = 0 to 7) 0 interrupt request signal did not occur at falling edge 1 interrupt request signal occurred at falling edge remark n = 0: control of nmi pin n = 1 to 7: control of intp0 to intp6 pins (4) block diagram (port 0) figure 5-1. block diagram of p00 to p07 wr pm wr port rd p00/nmi p01/intp0 p02/intp1 p03/intp2 p04/intp3 p05/intp4/adtrg p06/intp5 p07/intp6 selector output latch (p0n) pm0n pm0 internal bus remarks 1. pm0: port 0 mode register rd: port 0 read signal wr: port 0 write signal 2. n = 0 to 7
chapter 5 port function user?s manual u14665ej2v0um 108 5.2.2 port 1 port 1 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. bits 0 and 2 are selectable as normal outputs or n-ch open-drain outputs. after reset: 00h r/w address: fffff002h 76543210 p1 0 0 p15 p14 p13 p12 p11 p10 p1n control of output data (in output mode) (n = 0 to 5) 0 outputs 0 1 outputs 1 remark in input mode: when p1 is read, the pin levels at that time are read. writing to p1 writes the values to that register. this does not affect the input pins. in output mode: when p1 is read, the values of p1 are read. writing to p1 writes the values to that register, and those values are immediately output. port 1 includes the following alternate functions. table 5-3. port 1 alternate function pins pin name alternate function i/o pull note remark port 1 p10 si0/sda0 i/o no selectable as n-ch open-drain output p11 so0 ? p12 sck0/scl0 selectable as n-ch open-drain output p13 si1/rxd0 p14 so1/txd0 p15 sck1/asck0 ? note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 109 (1) function of p1 pins port 1 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 1 mode register (pm1). in output mode, the values set to each bit are output to port 1 (p1). the port 1 function register (pf1) can be used to specify whether p10 and p12 are normal outputs or n-ch open-drain outputs. when using this port in input mode, the pin statuses can be read by reading p1. also, the values of p1 (output latch) can be read by reading p1 while in output mode. clear p1 and the pm1 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 1 mode register (pm1) pm1 can be read/written in 8- or 1-bit units. after reset: 3fh r/w address: fffff022h 76543210 pm1 0 0 pm15 pm14 pm13 pm12 pm11 pm10 pm1n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode (b) port 1 function register (pf1) pf1 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff0a2h 76543210 pf1 00000pf120pf10 pf1n control of normal output/n-ch open-drain output (n = 0, 2) 0 normal output 1 n-ch open-drain output
chapter 5 port function user?s manual u14665ej2v0um 110 (3) block diagram (port 1) figure 5-2. block diagram of p10 and p12 wr pm wr pf wr port rd v dd selector pf1n pf1 pm1n pm1 p-ch n-ch internal bus output latch (p1n) alternate function p10/si0/sda0 p12/sck0/scl0 remarks 1. pf1: port 1 function register pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal 2. n = 0, 2
chapter 5 port function user?s manual u14665ej2v0um 111 figure 5-3. block diagram of p11 and p13 to p15 wr pm wr port rd selector output latch (p1n) pm1n pm1 internal bus alternate function p11/so0 p13/si1/rxd0 p14/so1/txd0 p15/sck1/asck0 remarks 1. pm1: port 1 mode register rd: port 1 read signal wr: port 1 write signal 2. n = 1, 3 to 5
chapter 5 port function user?s manual u14665ej2v0um 112 5.2.3 port 2 port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff004h 76543210 p2 p27 p26 p25 p24 p23 p22 p21 p20 p2n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p2 is read, the pin levels at that time are read. writing to p2 writes the values to that register. this does not affect the input pins. in output mode: when p2 is read, the values of p2 are read. writing to p2 writes the values to that register, and those values are immediately output. port 2 includes the following alternate functions. table 5-4. port 2 alternate function pins pin name alternate function i/o pull note remark port 2 p20 si3/rxd1 p21 so3/txd1 p22 sck3/asck1 p23 si4 p24 so4 p25 sck4 p26 ? p27 ? i/o no ? note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 113 (1) function of p2 pins port 2 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 2 mode register (pm2). in output mode, the values set to each bit are output to port 2 (p2). when using this port in input mode, the pin statuses can be read by reading p2. also, the values of p2 (output latch) can be read by reading p2 while in output mode. clear p2 and the pm2 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 2 mode register (pm2) pm2 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff024h 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode
chapter 5 port function user?s manual u14665ej2v0um 114 figure 5-4. block diagram of p20 to p25 wr pm wr port rd selector output latch (p2n) pm2n pm2 internal bus alternate function p20/si3/rxd1 p21/so3/txd1 p22/sck3/asck1 p23/si4 p24/so4 p25/sck4 remarks 1. pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 0 to 5 figure 5-5. block diagram of p26 and p27 wr pm wr port rd selector output latch (p2n) pm2n pm2 internal bus p26, p27 remarks 1. pm2: port 2 mode register rd: port 2 read signal wr: port 2 write signal 2. n = 6, 7
chapter 5 port function user?s manual u14665ej2v0um 115 5.2.4 port 3 port 3 is a 5-bit i/o port for which i/o settings can be controlled in 1-bit units. when using p30 to p33 as the ti2 to ti5 pins, noise is eliminated by a digital eliminator. after reset: 00h r/w address: fffff006h 76543210 p3 0 0 0 p34 p33 p32 p31 p30 p3n control of output data (in output mode) (n = 0 to 4) 0 outputs 0 1 outputs 1 remark in input mode: when p3 is read, the pin levels at that time are read. writing to p3 writes the values to that register. this does not affect the input pins. in output mode: when p3 is read, the values of p3 are read. writing to p3 writes the values to that register, and those values are immediately output. port 3 includes the following alternate functions. table 5-5. port 3 alternate function pins pin name alternate function i/o pull note remark p30 ti2/to2 p31 ti3/to3 p32 ti4/to4 p33 ti5/to5 digital noise elimination port 3 p34 vm45/ti71 i/o no ? note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 116 (1) function of p3 pins port 3 is a 5-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 3 mode register (pm3). in output mode, the values set to each bit are output to port 3 (p3). when using this port in input mode, the pin statuses can be read by reading p3. also, the values of p3 (output latch) can be read by reading p3 while in output mode. when using the alternate function as ti2 to ti5 pins, noise is eliminated by the digital noise eliminator (same as the digital noise eliminator for port 0). clear p3 and the pm3 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when using the alternate-function vm45 pin, set this port via the vm45 control register (vm45c). in this case, be sure to set p34 and pm34 to 0. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 3 mode register (pm3) pm3 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff026h 76543210 pm3 0 0 0 pm34 pm33 pm32 pm31 pm30 pm3n control of i/o mode (n = 0 to 4) 0 output mode 1 input mode
chapter 5 port function user?s manual u14665ej2v0um 117 (3) block diagram (port 3) figure 5-6. block diagram of p30 to p34 wr pm wr port rd selector output latch (p3n) pm3n pm3 internal bus alternate function p30/ti2/to2 p31/ti3/to3 p32/ti4/to4 p33/ti5/to5 p34/vm45/ti71 remarks 1. pm3: port 3 mode register rd: port 3 read signal wr: port 3 write signal 2. n = 0 to 4
chapter 5 port function user?s manual u14665ej2v0um 118 5.2.5 ports 4 and 5 ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff008h, fffff00ah 76543210 pn pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 (n = 4, 5) pnx control of output data (in output mode) (n = 4, 5, x = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p4 and p5 are read, the pin levels at that time are read. writing to p4 and p5 writes the values to those registers. this does not affect the input pins. in output mode: when p4 and p5 are read, their values are read. writing to p4 and p5 writes the values to those registers, and those values are immediately output. ports 4 and 5 include the following alternate functions. table 5-6. alternate function pins of ports 4 and 5 pin name alternate function i/o pull note remark port 4 p40 ad0 i/o no ? p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 ad7 port 5 p50 ad8 i/o no ? p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 ad15 note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 119 (1) functions of p4 and p5 pins ports 4 and 5 are 8-bit i/o ports for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via port 4 mode register (pm4) and port 5 mode register (pm5). in output mode, the values set to each bit are output to the port 4 and port 5 (p4 and p5). when using these ports in input mode, the pin statuses can be read by reading p4 and p5. also, the values of p4 and p5 (output latch) can be read by reading p4 and p5 while in output mode. a software pull-up function is not implemented. when using the p4 and p5 pins as ad0 to ad15, set the pin functions via the memory expansion mode register (mm). this does not affect the pm4 and pm5 registers. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 4 mode register and port 5 mode register (pm4 and pm5) pm4 and pm5 can be read/written in 8- or 1-bit units. after reset: ff h r/w address: fffff028h, fffff02ah 76543210 pmn pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 (n = 4, 5) pmnx control of i/o mode (n = 4, 5, x = 0 to 7) 0 output mode 1 input mode
chapter 5 port function user?s manual u14665ej2v0um 120 (3) block diagram (ports 4 and 5) figure 5-7. block diagram of p40 to p47 and p50 to p57 wr pm wr port rd selector output latch (pmn) pmmn pmm internal bus pmn/adx remarks 1. pmm: port m mode register rd: port m read signal wr: port m write signal 2. m = 4, 5 n = 0 to 7 x = 0 to 15
chapter 5 port function user?s manual u14665ej2v0um 121 5.2.6 port 6 port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff00ch 76543210 p6 0 0 p65 p64 p63 p62 p61 p60 p6n control of output data (in output mode) (n = 0 to 5) 0 outputs 0 1 outputs 1 remark in input mode: when p6 is read, the pin levels at that time are read. writing to p6 writes the values to that register. this does not affect the input pins. in output mode: when p6 is read, the values of p6 are read. writing to p6 writes the values to that register, and those values are immediately output. port 6 includes the following alternate functions. table 5-7. port 6 alternate function pins pin name alternate function i/o pull note remark port 6 p60 a16 i/o no ? p61 a17 p62 a18 p63 a19 p64 a20 p65 a21 note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 122 (1) function of p6 pins port 6 is a 6-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 6 mode register (pm6). in output mode, the values set to each bit are output to port 6 (p6). when using this port in input mode, the pin statuses can be read by reading p6. also, the values of p6 (output latch) can be read by reading p6 while in output mode. a software pull-up function is not implemented. when using the alternate function as a16 to a21, set the pin functions via the memory expansion mode register (mm). this does not affect the pm6 register. when a reset is input, the settings are initialized to input mode. (2) control register (a) port 6 mode register (pm6) pm6 can be read/written in 8- or 1-bit units. after reset: 3fh r/w address: fffff02ch 76543210 pm6 0 0 pm65 pm64 pm63 pm62 pm61 pm60 pm6n control of i/o mode (n = 0 to 5) 0 output mode 1 input mode
chapter 5 port function user?s manual u14665ej2v0um 123 (3) block diagram (port 6) figure 5-8. block diagram of p60 to p65 wr pm wr port rd selector output latch (p6n) pm6n pm6 internal bus p6n/ax remarks 1. pm6: port 6 mode register rd: port 6 read signal wr: port 6 write signal 2. n = 0 to 5 x = 16 to 21
chapter 5 port function user?s manual u14665ej2v0um 124 5.2.7 ports 7 and 8 port 7 is an 8-bit input port and port 8 is a 4-bit input port. both ports are read-only and are accessible in 8- or 1- bit units. after reset: undefined r address: fffff00eh 76543210 p7 p77 p76 p75 p74 p73 p72 p71 p70 p7n pin level (n = 0 to 7) 0/1 read pin level of bit n after reset: undefined r address: fffff010h 76543210 p8 0 0 0 0 p83 p82 p81 p80 p8n pin level (n = 0 to 3) 0/1 read pin level of bit n ports 7 and 8 include the following alternate functions. table 5-8. alternate function pins of ports 7 and 8 pin name alternate function i/o pull note remark port 7 p70 ani0 input no ? p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 port 8 p80 ani8 input no ? p81 ani9 p82 ani10 p83 ani11 note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 125 (1) functions of p7 and p8 pins port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. the pin statuses can be read by reading port 7 and port 8 (p7 and p8). data cannot be written to p7 or p8. a software pull-up function is not implemented. values read from pins specified as analog inputs are undefined values. do not read values from p7 or p8 during a/d conversion. (2) block diagram (ports 7 and 8) figure 5-9. block diagram of p70 to p77 and p80 to p83 pmn/anix rd internal bus remarks 1. rd: port 7, port 8 read signals 2. m = 7, 8 n = 0 to 7 (m = 7), 0 to 3 (m = 8) x = 0 to 7 (m = 7), 8 to 11 (m = 8)
chapter 5 port function user?s manual u14665ej2v0um 126 5.2.8 port 9 port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. after reset: 00h r/w address: fffff012h 76543210 p9 0 p96 p95 p94 p93 p92 p91 p90 p9n control of output data (in output mode) (n = 0 to 6) 0 outputs 0 1 outputs 1 remark in input mode: when p9 is read, the pin levels at that time are read. writing to p9 writes the values to that register. this does not affect the input pins. in output mode: when p9 is read, the values of p9 are read. writing to p9 writes the values to that register, and those values are immediately output. port 9 includes the following alternate functions. table 5-9. port 9 alternate function pins pin name alternate function i/o pull note remark p90 lben p91 uben p92 r/w p93 dstb p94 astb p95 hldak port 9 p96 hldrq i/o no ? note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 127 (1) function of p9 pins port 9 is a 7-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 9 mode register (pm9). in output mode, the values set to each bit are output to port 9 (p9). when using this port in input mode, the pin statuses can be read by reading p9. also, the values of p9 (output latch) can be read by reading p9 while in output mode. a software pull-up function is not implemented. when using p9 for control signals in expansion mode, set the pin functions via the memory expansion mode register (mm). when a reset is input, the settings are initialized to input mode. (2) control register (a) port 9 mode register (pm9) pm9 can be read/written in 8- or 1-bit units. after reset: 7fh r/w address: fffff032h 76543210 pm9 0 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n control of i/o mode (n = 0 to 6) 0 output mode 1 input mode
chapter 5 port function user?s manual u14665ej2v0um 128 (3) block diagram (port 9) figure 5-10. block diagram of p90 to p96 wr pm wr port rd selector output latch (p9n) pm9n pm9 internal bus p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq remarks 1. pm9: port 9 mode register rd: port 9 read signal wr: port 9 write signal 2. n = 0 to 6
chapter 5 port function user?s manual u14665ej2v0um 129 5.2.9 port 10 port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. a pull-up resistor can be connected in 1-bit units (software pull-up function). when using p100 to p107 as the kr0 to kr7 pins, noise is eliminated by an analog noise eliminator. after reset: 00h r/w address: fffff014h 76543210 p10 p107 p106 p105 p104 p103 p102 p101 p100 p10n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p10 is read, the pin levels at that time are read. writing to p10 writes the values to that register. this does not affect the input pins. in output mode: when p10 is read, the values of p10 are read. writing to p10 writes the values to that register, and those values are immediately output. port 10 includes the following alternate functions. table 5-10. port 10 alternate function pins pin name alternate function i/o pull note remark port 10 p100 kr0/to7 i/o yes p101 kr1/ti70 p102 kr2/ti00 p103 kr3/ti01 p104 kr4/to0 p105 kr5/ti10 p106 kr6/ti11 p107 kr7/to1 analog noise elimination note software pull-up function
chapter 5 port function user?s manual u14665ej2v0um 130 (1) function of p10 pins port 10 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 10 mode register (pm10). in output mode, the values set to each bit are output to port 10 (p10). when using this port in input mode, the pin statuses can be read by reading p10. also, the values of p10 (output latch) can be read by reading p10 while in output mode. a pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 10 (pu10). when used as kr0 to kr7 pins, noise is eliminated by an analog noise eliminator. clear p10 and the pm10 register to 0 when using alternate-function pins as outputs. the logical sum (ored result) of the port output and the alternate-function pin is output from the pins. when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 10 mode register (pm10) pm10 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff034h 76543210 pm10 pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 pm10n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) pull-up resistor option register 10 (pu10) pu10 can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff094h 76543210 pu10 pu107 pu106 pu105 pu104 pu103 pu102 pu101 pu100 pu10n control of on-chip pull-up resistor connection (n = 0 to 7) 0 do not connect 1 connect
chapter 5 port function user?s manual u14665ej2v0um 131 (3) block diagram (port 10) figure 5-11. block diagram of p100 to p107 p-ch wr pm wr port rd wr pu v dd selector pm10n pm10 pu10n pu10 internal bus output latch (p10n) alternate function p100/kr0/to7 p101/kr1/ti70 p102/kr2/ti00 p103/kr3/ti01 p104/kr4/to0 p105/kr5/ti10 p106//kr6/ti11 p107/kr7/to1 remarks 1. pu10: pull-up resistor option register 10 pm10: port 10 mode register rd: port 10 read signal wr: port 10 write signal 2. n = 0 to 7
chapter 5 port function user?s manual u14665ej2v0um 132 5.2.10 port 11 port 11 is an 8-bit i/o port for which i/o settings can be controlled in 1-bit units. p11 can be read/written in 8- or 1-bit units. turning on and off the wait function and switching between alternate pins and port pins can be performed via the port alternate-function control register (pac) (cantx2 and canrx2 are available only for the pd703079y and 70f3079y). after reset: 00h r/w address: fffff016h 76543210 p11 p117 p116 p115 p114 p113 p112 p111 p110 p11n control of output data (in output mode) (n = 0 to 7) 0 outputs 0 1 outputs 1 remark in input mode: when p11 is read, the pin levels at that time are read. writing to p11 writes the values to that register. this does not affect the input pins. in output mode: when p11 is read, the values of p11 are read. writing to p11 writes the values to that register, and those values are immediately output. port 11 includes the following alternate functions. table 5-11. port 11 alternate function pins pin name alternate function i/o pull note 1 remark p110 wait p111 ? p112 ? p113 ? p114 cantx1 p115 canrx1 p116 cantx2 note 2 port 11 p117 canrx2 note 2 i/o no ? notes 1. software pull-up function 2. only for the pd703079y and 70f3079y
chapter 5 port function user?s manual u14665ej2v0um 133 (1) function of p11 pins port 11 is an 8-bit port for which i/o settings can be controlled in 1-bit units. i/o settings are controlled via the port 11 mode register (pm11). in output mode, the values set to each bit are output to port 11 (p11). when using this port in input mode, the pin statuses can be read by reading p11. also, the values of p11 (output latch) can be read by reading p11 while in output mode. turning on and off the wait function and switching between alternate pins and port pins can be performed via the port alternate-function control register (pac). when a reset is input, the settings are initialized to input mode. (2) control registers (a) port 11 mode register (pm11) pm11 can be read/written in 8- or 1-bit units. after reset: ffh r/w address: fffff036h 76543210 pm11 pm117 pm116 pm115 pm114 pm113 pm112 pm111 pm110 pm11n control of i/o mode (n = 0 to 7) 0 output mode 1 input mode (b) port alternate-function control register (pac) pac can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff040h 76543210 pac pac117 note pac116 note pac115 pac114 0 0 0 wac wac control of wait function 0 wait function off 1 wait function on pac11n control of port alternate function (n = 4 to 7) 0 port function 1 alternate function note bits pac117 and pac116 are available only for the pd703079y and 70f3079y. set bits 7 and 6 to 0 when using the pd703078y.
chapter 5 port function user?s manual u14665ej2v0um 134 (3) block diagram (port 11) figure 5-12. block diagram of p110 and p114 to p117 remarks 1. pm11: port 11 mode register rd: port 11 read signal wr: port 11 write signal pac: port alternate-function control register (pac) 2. n = 0, 4 to 7 m = 4 to 7 rd wr port wr pm output latch (p11n) pm11n pm11 pac11m, wac pac selector p110/wait p114/cantx1 p115/canrx1 p116/cantx2 p117/canrx2 alternate function selector internal bus
chapter 5 port function user?s manual u14665ej2v0um 135 figure 5-13. block diagram of p111 to p113 wr pm wr port rd selector output latch (p11n) pm11n pm11 internal bus p111 to p113 remarks 1. pm11: port 11 mode register rd: port 11 read signal wr: port 11 write signal 2. n = 1 to 3
chapter 5 port function user?s manual u14665ej2v0um 136 5.3 setting when port pin is used for alternate function when a port pin is used for an alternate function, set the port n mode register (pm0 to pm6 and pm9 to pm11) and output latch as shown in table 5-12 below. table 5-12. setting when port pin is used for alternate function (1/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p00 nmi input pm00 = 1 setting not needed for p00 ? p01 intp0 input pm01 = 1 setting not needed for p01 ? p02 intp1 input pm02 = 1 setting not needed for p02 ? p03 intp2 input pm03 = 1 setting not needed for p03 ? p04 intp3 input pm04 = 1 setting not needed for p04 ? intp4 input p05 adtrg input pm05 = 1 setting not needed for p05 ? p06 intp5 input pm06 = 1 setting not needed for p06 ? p07 intp6 input pm07 = 1 setting not needed for p07 ? si0 input pm10 = 1 setting not needed for p10 p10 sda0 i/o pm10 = 0 p10 = 0 ? p11 so0 output pm11 = 0 p11 = 0 ? input pm12 = 1 setting not needed for p12 sck0 output p12 scl0 i/o pm12 = 0 p12 = 0 ? si1 input p13 rxd0 input pm13 = 1 setting not needed for p13 ? so1 output p14 txd0 output pm14 = 0 p14 = 0 ? input pm15 = 1 setting not needed for p15 sck1 output pm15 = 0 p15 = 0 p15 asck0 input pm15 = 1 setting not needed for p15 ?
chapter 5 port function user?s manual u14665ej2v0um 137 table 5-12. setting when port pin is used for alternate function (2/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) si3 input p20 rxd1 input pm20 = 1 setting not needed for p20 ? so2 output p21 txd1 output pm21 = 0 p21 = 0 ? input pm22 = 1 setting not needed for p22 sck3 output pm22 = 0 p22 = 0 p22 asck1 input pm22 = 1 setting not needed for p22 ? p23 si4 input pm23 = 1 setting not needed for p23 ? p24 so4 output pm24 = 0 p24 = 0 ? input pm25 = 1 setting not needed for p25 p25 sck4 output pm25 = 0 p25 = 0 ? ti2 input pm30 = 1 setting not needed for p30 p30 to2 output pm30 = 0 p30 = 0 ? ti3 input pm31 = 1 setting not needed for p31 p31 to3 output pm31 = 0 p31 = 0 ? ti4 input pm32 = 1 setting not needed for p32 p32 to4 output pm32 = 0 p32 = 0 ? ti5 input pm33 = 1 setting not needed for p33 p33 to5 output pm33 = 0 p33 = 0 ? ti71 input pm34 = 1 setting not needed for p34 ? p34 vm45 output pm34 = 0 p34 = 0 note note refer to 14.3 (2) vm45 control register (vm45c).
chapter 5 port function user?s manual u14665ej2v0um 138 table 5-12. setting when port pin is used for alternate function (3/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) p40 to p47 ad0 to ad7 i/o setting not needed for pm40 to pm47 setting not needed for p40 to p47 note p50 to p57 ad8 to ad15 i/o setting not needed for pm50 to pm57 setting not needed for p50 to p57 note p60 to p65 a16 to a21 output setting not needed for pm60 to pm65 setting not needed for p60 to p65 note p70 to p77 ani0 to ani7 input none setting not needed for p70 to p77 ? p80 to p83 ani8 to ani11 input none setting not needed for p80 to p83 ? p90 lben output setting not needed for pm90 setting not needed for p90 note p91 uben output setting not needed for pm91 setting not needed for p91 note p92 r/w output setting not needed for pm92 setting not needed for p92 note p93 dstb output setting not needed for pm93 setting not needed for p93 note p94 astb output setting not needed for pm94 setting not needed for p94 note p95 hldak output setting not needed for pm95 p95 = 1 note p96 hldrq input setting not needed for pm96 p96 = 1 note note refer to 3.4.6 (1) memory expansion mode register (mm).
chapter 5 port function user?s manual u14665ej2v0um 139 table 5-12. setting when port pin is used for alternate function (4/4) alternate function pin name function name i/o pmnx bit of pmn register pnx bit of pn register other bits (register) kr0 input pm 100 = 1 setting not needed for p100 p100 to7 output pm100 = 0 p100 = 0 ? kr1 input p101 ti70 input pm101 = 1 setting not needed for p101 ? kr2 input p102 ti00 input pm102 = 1 setting not needed for p102 ? kr3 input p103 ti01 input pm103 = 1 setting not needed for p103 ? kr4 input pm 104 = 1 setting not needed for p104 p104 to0 output pm104 = 0 p104 = 0 ? kr5 input p105 ti10 input pm105 = 1 setting not needed for p105 ? kr6 input p106 ti11 input pm106 = 1 setting not needed for p106 ? kr7 input pm 107 = 1 setting not needed for p107 p107 to1 output pm107 = 0 p107 = 0 ? p110 wait input pm110 = 1 setting not needed for p110 wac = 1 (pac) p114 cantx1 output pm114 = 0 p 114 = 0 pac 114 = 1 (pac) p115 canrx1 input pm 115 = 1 p 115 = 0 pac 115 = 1 (pac) p116 cantx2 note output pm116 = 0 p 116 = 0 pac 116 = 1 (pac) p117 canrx2 note input pm 117 = 1 p 117 = 0 pac 117 = 1 (pac) note only for the pd703079y and 70f3079y. cautions 1. when changing the output level of port 0 by setting the port function output mode of port 0, the interrupt request flag will be set because port 0 also has an alternate function as external interrupt request input. therefore, be sure to set the corresponding interrupt mask flag to 1 before using a port 0 pin as an output pin. 2. when using the i 2 c bus mode, be sure to specify n-ch open-drain output for the sda0/p10 and scl0/p12 pins by setting the port 1 function register (pf1). remark pmnx bit of pmn register and pnx bit of pn register n: 0 (x = 0 to 7) n: 1 (x = 0 to 5) n: 2 (x = 0 to 7) n: 3 (x = 0 to 4) n: 4 (x = 0 to 7) n: 5 (x = 0 to 7) n: 6 (x = 0 to 5) n: 7 (x = 0 to 7) n: 8 (x = 0 to 3) n: 9 (x = 0 to 6) n: 10 (x = 0 to 7) n: 11 (x = 0 to 7)
140 user?s manual u14665ej2v0um chapter 6 bus control function the v850/sf1 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 6.1 features ? address bus ? 16-bit data bus ? able to be connected to external devices via pins with alternate-functions as ports ? wait function ? programmable wait function, capable of inserting up to 3 wait states per 2 blocks ? external wait control through wait input pin ? idle state insertion function ? bus mastership arbitration function ? bus hold function 6.2 bus control pins and control register 6.2.1 bus control pins the following pins are used for interfacing with external devices. table 6-1. bus control pins external bus interface function corresponding port (pins) address/data bus (ad0 to ad7) port 4 (p40 to p47) address/data bus (ad8 to ad15) port 5 (p50 to p57) address bus (a16 to a21) port 6 (p60 to p65) read/write control (lben, uben, r/w, dstb) port 9 (p90 to p93) address strobe (astb) port 9 (p94) bus hold control (hldrq, hldak) port 9 (p95, p96) external wait control (wait) port 11 (p110) the bus interface function of each pin is enabled by setting the memory expansion mode register (mm). for details of external bus interface operating mode specification, refer to 3.4.6 (1) memory expansion mode register (mm).
chapter 6 bus control function user?s manual u14665ej2v0um 141 6.3 bus access 6.3.1 number of access clocks the number of basic clocks necessary for accessing each resource is as follows. table 6-2. number of access clocks peripheral i/o (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) peripheral i/o (16 bits) external memory (16 bits) instruction fetch 1 3 disabled 3 + n operand data access 3 1 3 3 + n remarks 1. unit: clock/access 2. n: number of wait insertions
chapter 6 bus control function user?s manual u14665ej2v0um 142 6.3.2 bus width the cpu carries out peripheral i/o access and external memory access in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each access. (1) byte access (8 bits) byte access is divided into two types: access to even addresses and access to odd addresses. figure 6-1. byte access (8 bits) 0 7 0 7 8 15 byte data external data bus (a) access to even address 0 7 0 7 8 15 byte data external data bus (b) access to odd address (2) halfword access (16 bits) in halfword access to external memory, data is handled as is because the data bus is fixed to 16 bits. figure 6-2. halfword access (16 bits) 00 15 15 halfword data external data bus (3) word access (32 bits) in word access to external memory, the lower halfword is accessed first and then the higher halfword is accessed. figure 6-3. word access (32 bits) 0 15 0 15 16 31 word data external data bus first 0 15 0 15 16 31 word data external data bus second
chapter 6 bus control function user?s manual u14665ej2v0um 143 6.4 memory block function the 16 mb memory space is divided into memory blocks of 1 mb units. the programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. figure 6-4. memory block block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 internal peripheral i/o area internal ram area external memory area ffffffh f00000h efffffh e00000h dfffffh d00000h cfffffh c00000h bfffffh b00000h afffffh a00000h 9fffffh 900000h 8fffffh 800000h 7fffffh 700000h 6fffffh 600000h 5fffffh 500000h 4fffffh 400000h 3fffffh 300000h 2fffffh 200000h 1fffffh 100000h 0fffffh 000000h internal rom area
chapter 6 bus control function user?s manual u14665ej2v0um 144 6.5 wait function 6.5.1 programmable wait function to facilitate interfacing with low-speed memories and i/o devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. the number of wait states can be programmed by using the data wait control register (dwc). immediately after the system has been reset, three data wait states are automatically programmed for insertion in all memory blocks. (1) data wait control register (dwc) this register can be read/written in 16-bit units. after reset: ffffh r/w address: fffff060h 1514131211109876543210 dwc number of wait states to be inserted 00 0 01 1 10 2 11 3 n blocks into which wait states are inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area. it is not subject to programmable wait control, regardless of the setting of dwc, and is always accessed without wait states. the internal ram area of block 15 is not subject to programmable wait control and is always accessed without wait states. the on-chip peripheral i/o area of this block is not subject to programmable wait control, either. the wait control is dependent upon the execution of each peripheral function. dw61 dw00 dw01 dw10 dw11 dw20 dw21 dw30 dw31 dw40 dw41 dw50 dw51 dw60 dw70 dw71 dwn0 dwn1
chapter 6 bus control function user?s manual u14665ej2v0um 145 6.5.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (wait) to synchronize with the external device. the external wait signal is for data wait only, and does not affect the access times of the internal rom, internal ram, and on-chip peripheral i/o areas, similar to programmable wait. the external wait signal can be input asynchronously to clkout and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the setup/hold time at the sampling timing is not satisfied, the wait state may or may not be inserted in the next state. caution the p110 pin and wait pin are alternate-function pins. set bit 0 (wac) of the port alternate function control register (pac) to 1 when these pins are used for the wait function. 6.5.3 relationship between programmable wait and external wait a wait cycle is inserted as a result of an or operation between the wait cycle specified by the set value of a programmable wait and the wait cycle controlled by the wait pin. in other words, the number of wait cycles is determined by whichever has more cycles. figure 6-5. wait control wait control programmable wait wait by wait pin for example, if the number of programmable waits and the timing of the wait pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 6-6. example of inserting wait states clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark { : valid sampling timing
chapter 6 bus control function user?s manual u14665ej2v0um 146 6.6 idle state insertion function to facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (ti) can be inserted into the current bus cycle after the t3 state. the bus cycle following continuous bus cycles starts after one idle state. specifying insertion of the idle state is programmable by using the bus cycle control register (bcc). immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. after reset: aaaah r/w address: fffff062h 1514131211109876543210 bcc idle state insert specification 0 not inserted 1 inserted n blocks into which idle state is inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 block 0 is reserved for the internal rom area and therefore no idle state can be specified. the internal ram area and on-chip peripheral i/o area of block 15 are not subject to insertion of an idle state. be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. if these bits are set to 1, the operation is not guaranteed. 0 bc01 0 bc11 0 bc21 0 bc31 0 bc41 0 bc51 0 bc61 0 bc71 bcn1
chapter 6 bus control function user?s manual u14665ej2v0um 147 6.7 bus hold function 6.7.1 outline of function when the mm3 bit of the memory expansion mode register (mm) is set (1), the hldrq and hldak pin functions of p95 and p96 become valid. when the hldrq pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state, and the bus is released (bus hold status). when the hldrq pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. during the bus hold period, the internal operation continues until the next external memory access. the bus hold status can be recognized by the hldak pin becoming active (low). this feature can be used to design a system where two or more bus masters exist, such as when a multi- processor configuration is used and when a dma controller is connected. bus hold requests are not acknowledged between the first and the second word access, nor between a read access and a write access in the read modify write access of a bit manipulation instruction.
chapter 6 bus control function user?s manual u14665ej2v0um 148 6.7.2 bus hold procedure the procedure of the bus hold function is illustrated below. figure 6-7. bus hold procedure 6.7.3 operation in power save mode in the stop or idle mode, the system clock is stopped. consequently, the bus hold status is not set even if the hldrq pin becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold status is set. when the hldrq pin becomes inactive, the hldak pin becomes inactive. as a result, the bus hold status is cleared, and the halt mode is set again. hldrq hldak < 1 >< 2 >< 3 >< 4 >< 5 >< 7 >< 8 >< 9 > < 6 > <1>hldrq = 0 acknowledged <2>all bus cycle start requests pending <3>end of current bus cycle <4>bus idle status <5>hldak = 0 <6>hldrq = 1 acknowledged <7>hldak = 1 <8>clears bus cycle start requests pending <9>start of bus cycle nomal status bus hold status normal status
chapter 6 bus control function user?s manual u14665ej2v0um 149 6.8 bus timing the v850/sf1 can execute read/write control for an external device using the following mode. ? mode using dstb, r/w, lben, uben, and astb signals figure 6-8. memory read (1/4) (a) 0 waits remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 t3 clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address data address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input)
chapter 6 bus control function user?s manual u14665ej2v0um 150 figure 6-8. memory read (2/4) (b) 1 wait remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) t3 data
chapter 6 bus control function user?s manual u14665ej2v0um 151 figure 6-8. memory read (3/4) (c) 0 waits, idle state remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 t3 clkout (output) ad0 to ad15 (i/o) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) ti data a16 to a21 (output) address
chapter 6 bus control function user?s manual u14665ej2v0um 152 figure 6-8. memory read (4/4) (d) 1 wait, idle state remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 tw clkout (output) ad0 to ad15 (i/o) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) t3 data ti a16 to a21 (output) address
chapter 6 bus control function user?s manual u14665ej2v0um 153 figure 6-9. memory write (1/2) (a) 0 waits note ad0 to ad7 output invalid data when odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 t3 clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address data note address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input)
chapter 6 bus control function user?s manual u14665ej2v0um 154 figure 6-9. memory write (2/2) (b) 1 wait note ad0 to ad7 output invalid data when odd-address byte data is accessed. ad8 to ad15 output invalid data when even-address byte data is accessed. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. t1 t2 tw clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) address astb (output) r/w (output) dstb (output) uben, lben (output) wait (input) t3 data note address
chapter 6 bus control function user?s manual u14665ej2v0um 155 figure 6-10. bus hold timing notes 1. if the hldrq signal is inactive (high level) at this sampling timing, the bus hold state is not entered. 2. if transferred to the bus hold states after a write cycle, a high level may be output momentarily from the r/w pin immediately before the hldak signal changes from high level to low level. remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0. 2. the broken lines indicate the high-impedance state. clkout (output) r/w (output) dstb (output) uben, lben (output) wait (input) hldrq (input) t2 t3 th th th th ti t1 hldak (output) a16 to a21 (output) ad0 to ad15 (i/o) address address data address astb (output) undefined address note 1 note 2
chapter 6 bus control function user?s manual u14665ej2v0um 156 6.9 bus priority there are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). the bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order. the instruction fetch cycle may be inserted in between a read access and a write access in a read-modify-write access. no instruction fetch cycle and bus hold are inserted between the lower halfword access and the higher halfword access in word access operations. table 6-3. bus priority external bus cycle priority bus hold 1 operand data access 2 instruction fetch (branch) 3 instruction fetch (continuous) 4 6.10 memory boundary operation condition 6.10.1 program space (1) do not execute a branch to the on-chip peripheral i/o area or a continuous fetch from the internal ram area to the peripheral i/o area. if a branch or instruction fetch is executed, the nop instruction code is continuously fetched and fetching from external memory is not performed. (2) a prefetch operation extending over the on-chip peripheral i/o area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal ram area. 6.10.2 data space only the address aligned at the halfword boundary (when the least significant bit of the address is ?0?)/word boundary (when the lowest 2 bits of the address are ?0?) is accessed by halfword (16 bits)/word (32 bits) access, respectively. therefore, access that extends over the memory or memory block boundary does not take place. for details, refer to v850 family user?s manual architecture .
user?s manual u14665ej2v0um 157 chapter 7 interrupt/exception processing function 7.1 outline the v850/sf1 is provided with a dedicated interrupt controller (intc) for interrupt servicing and realizes a high- powered interrupt function that can service interrupt requests from a total of 41 sources ( pd703078y)/44 sources ( pd70f3079y, 703079y). an interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependent on program execution. the v850/sf1 can service interrupt requests from the internal peripheral hardware and external sources. moreover, exception processing can be started (exception trap) by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code). 7.1.1 features ? interrupts ? non-maskable interrupts: 2 sources ? maskable interrupts (the number of maskable interrupt sources differs depending on product): pd703078y: 41 sources pd703079y, 70f3079y: 44 sources ? 8 levels of programmable priorities ? mask specification for interrupt requests according to priority ? masks can be specified for each maskable interrupt request. ? noise elimination, edge detection, and the valid edge of an external interrupt request signal can be specified. ? exceptions ? software exceptions: 32 sources ? exception trap: 1 source (illegal op code exception) the interrupt/exception sources are listed in table 7-1.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 158 table 7-1. interrupt source list (1/2) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset interrupt ? reset reset input ? 0000h 00000000h u ndefined ? interrupt ? nmi nmi pin input ? 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdtovf non-maskable wdt 0020h 00000020h nextpc ? exception ? trap0n note trap instruction ? 004nh note 00000040h nextpc ? software exception exception ? trap1n note trap instruction ? 005nh note 00000050h nextpc ? exception trap exception ? ilgop illegal op code ? 0060h 00000060h nextpc ? 0 intwdtm wdtovf maskable wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin pin 00f0h 000000f0h nextpc pic6 8 intcsi4 csi4 transmit end sio4 0100h 00000100h nextpc csic4 9 intad a/d conversion end a/d 0110h 00000110h nextpc adic 10 intdma0 dma0 transfer end dma0 0120h 00000120h nextpc dma0 11 intdma1 dma1 transfer end dma1 0130h 00000130h nextpc dma1 12 intdma2 dma2 transfer end dma2 0140h 00000140h nextpc dma2 13 inttm00 tm0 and cr00 match/ ti00 pin valid edge tm0 0150h 00000150h nextpc tmic00 14 inttm01 tm1 and cr01 match/ ti01 pin valid edge tm0 0160h 00000160h nextpc tmic01 15 inttm10 tm1 and cr10 match/ ti00 pin valid edge tm1 0170h 00000170h nextpc tmic10 16 inttm11 tm1 and cr11 match/ ti11 pin valid edge tm1 0180h 00000180h nextpc tmic11 17 inttm2 tm2 compare match/ovf tm2 0190h 00000190h nextpc tmic2 18 inttm3 tm3 compare match/ovf tm3 01a0h 000001a0h nextpc tmic3 19 inttm4 tm4 compare match/ovf tm4 01b0h 000001b0h nextpc tmic4 20 inttm5 tm5 compare match/ovf tm5 01c0h 000001c0h nextpc tmic3 21 intwtn watch timer ovf wt 01d0h 000001d0h nextpc wtnic 22 intwtni watch timer prescaler wtn 01e0h 000001e0h nextpc wtniic 23 intiic0/ intcsi0 i 2 c interrupt/ csi0 transmit end i 2 c/ csi0 01f0h 000001f0h nextpc csic0 24 intser0 uart0 serial error uart0 0200h 00000200h nextpc seric0 25 intsr0/ intcsi1 uart0 receive end/ csi1 transmit end uart0/ csi1 0210h 00000210h nextpc csic1 maskable interrupt 26 intst0 uart0 transmit end uart0 0220h 00000220h nextpc stic0 note n: 0 to fh
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 159 table 7-1. interrupt source list (2/2) type classifi- cation default priority name trigger interrupt source exception code handler address restored pc interrupt control register 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intce1 fcan1 serial error fcan1 0240h 00000240h nextpc canic1 29 intcr1 fcan1 reception fcan1 0250h 00000250h nextpc canic2 30 intct1 fcan1 transmission fcan1 0260h 00000260h nextpc canic3 31 intcme fcan memory access error fcan1/ 2 0270h 00000270h nextpc canic7 32 inttm6 tm6 compare match/ ovf tm6 0280h 00000280h nextpc tmic6 33 inttm70 tm7 and cr70 match/ ti70 pin valid edge tm7 0290h 00000290h nextpc tmic70 34 inttm71 tm71 and cr71 match tm7 02a0h 000002a0h nextpc tmic71 35 intser1 uart1 serial error uart1 02b0h 000002b0h nextpc seric1 36 intsr1/ intcsi3 uart1 receive end/ csi3 transmit end uart1/ csi3 02c0h 000002c0h nextpc csic3 37 intst1 uart1 transmit end uart1 02d0h 000002d0h nextpc stic1 38 intdma3 dma3 transfer end dma3 02e0h 000002e0h nextpc dmaic3 39 intdma4 dma4 transfer end dma4 02f0h 000002f0h nextpc dmaic4 40 intdma5 dma5 transfer end dma5 0300h 00000300h nextpc dmaic5 41 intce2 note fcan2 serial error fcan2 0310h 00000310h nextpc canic4 42 intcr2 note fcan2 reception fcan2 0320h 00000320h nextpc canic5 maskable interrupt 43 intct2 note fcan2 transmission fcan2 0330h 00000330h nextpc canic6 note available only for the pd703079y and 70f3079y. remarks 1. default priority: the priority when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is acknowledged during the divh (division) instruction execution is the value of the pc of the current instruction (divh). 2. the execution address of the illegal instruction when an illegal op code exception occurs is calculated by (restored pc ? 4). 3. the restored pc of an interrupt/exception other than reset is the value of (the pc when an event occurred) + 1. 4. non-maskable interrupts (intwdt) and maskable interrupts (intwdtm) are set by the wdtm4 bit of the watchdog timer mode register (wdtm).
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 160 7.2 non-maskable interrupt a non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (di state). an nmi is not subject to priority control and takes precedence over all other interrupts. the following two non-maskable interrupt requests are available in the v850/sf1. ? nmi pin input (nmi) ? non-maskable watchdog timer interrupt request (intwdt) when the valid edge specified by the rising edge specification register (egp0) and falling edge specification register (egn0) is detected at the nmi pin, an interrupt occurs. intwdt functions as a non-maskable interrupt (intwdt) only when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 1. while the service routine of a non-maskable interrupt is being executed (psw.np = 1), the acknowledgement of another non-maskable interrupt request is held pending. the pending nmi is acknowledged after the original service routine of the non-maskable interrupt under execution has been terminated (by the reti instruction), or when psw.np is cleared to 0 by the ldsr instruction. note that if two or more nmi requests are input during the execution of the service routine for an nmi, only one nmi will be acknowledged after psw.np is cleared to 0. caution if psw.np is cleared to 0 by the ldsr instruction during non-maskable interrupt servicing, the interrupt afterwards cannot be acknowledged correctly.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 161 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine. (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher half-word (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) loads the handler address (00000010h, 00000020h) of the non-maskable interrupt routine to the pc, and transfers control. figure 7-1. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 00000010h, 00000020h intc acknowledged cpu processing psw. np 1 0
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 162 figure 7-2. acknowledging non-maskable interrupt requests (a) if a new nmi request is generated while an nmi service routine is being executed (b) if a new nmi request is generated twice while an nmi service routine is being executed main routine nmi request nmi request (psw. np = 1) nmi request held pending because psw. np = 1 pending nmi request serviced main routine nmi request nmi request held pending because nmi service program is being processed held pending because nmi service program is being processed nmi request only one nmi request is acknowledged even though two or more nmi requests are generated
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 163 7.2.2 restore execution is restored from non-maskable interrupt servicing by the reti instruction. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. (2) transfers control back to the address of the restored pc and psw. how the reti instruction is processed is shown below. figure 7-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during restoration by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 164 7.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt (nmi) servicing is under execution. this flag is set when an nmi interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. figure 7-4. np flag (np) after reset: 00000020h 31 876543210 psw 0 np ep id sat cy ov s z np nmi servicing state 0 no nmi interrupt servicing 1 nmi interrupt currently being serviced 7.2.4 noise eliminator of nmi pin nmi pin noise is eliminated by the noise eliminator using analog delay. therefore, a signal input to the nmi pin is not detected as an edge, unless it maintains its input level for a certain period. the edge is detected after a certain period has elapsed. the nmi pin is used for canceling the software stop mode. in the software stop mode, noise elimination using the system clock does not occur because the internal system clock is stopped.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 165 7.2.5 edge detection function of nmi pin the nmi pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, neither rising nor falling edge detected. rising edge specification register 0 (egp0) and falling edge specification register 0 (egn0) specify the valid edge of a non-maskable interrupt (nmi). these two registers can be read/written in 1-bit or 8-bit units. after reset, the valid edge of the nmi pin is set to the ?neither rising nor falling edge detected? state. therefore, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p00 as an output port, set the nmi valid edge to ?neither rising nor falling edge detected?. rising edge specification register 0 (egp0) after reset: 00h r/w address: fffff0c0h 76543210 egp0 egp07 egp06 egp05 egp04 egp03 egp02 egp01 egp00 egp0n rising edge valid control 0 no interrupt request signal occurs at the rising edge 1 interrupt request signal occurs at the rising edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control falling edge specification register 0 (egn0) after reset: 00h r/w address: fffff0c2h 76543210 egn0 egn07 egn06 egn05 egn04 egn03 egn02 egn01 egn00 egn0n falling edge valid control 0 no interrupt request signal occurs at the falling edge 1 interrupt request signal occurs at the falling edge n = 0: nmi pin control n = 1 to 7: intp0 to intp6 pins control
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 166 7.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850/sf1 has 41 ( pd703078y)/44 ( pd703079y, 70f3079y) maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupts is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt servicing routine, the interrupt enabled (ei) status is set, which enables interrupts having a higher priority to immediately interrupt the service routine in currently progress. note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to use multiple interrupts, it is necessary to save eipc and eipsw to memory or a register before executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm4 bit of the watchdog timer mode register (wdtm) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (intwdtm). 7.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower halfword of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) loads the corresponding handler address to the pc, and transfers control. the int input masked by intc and the int input that occurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally. when the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, the pending int is input to start new maskable interrupt servicing. how maskable interrupts are serviced is shown below.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 167 figure 7-5. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id pc intc acknowledged cpu processing mask? yes no psw. id = 0 priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? interrupt enable mode? restored pc psw exception code 0 1 handler address
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 168 7.3.2 restore to restore execution from maskable interrupt servicing, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of the pc and psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of psw is 0. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-6. reti instruction processing reti instruction restores original processing pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the maskable interrupt service, in order to restore the pc and psw correctly during restoration by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 169 7.3.3 priorities of maskable interrupts the v850/sf1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxprn). when two or more interrupts having the same priority level specified by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to table 7-1. programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of the psw is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag beforehand (for example, by placing the ei instruction into the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (wdt, p, wtni, tm, cs, ser, st, ad, dma, wtn, can, kr) n: peripheral unit number (see table 7-2 )
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 170 figure 7-7. example of interrupt nesting (1/2) caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 171 figure 7-7. example of interrupt nesting (2/2) notes 1. lower default priority 2. higher default priority main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 172 figure 7-8. example of servicing interrupt requests simultaneously generated main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b ?  servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. nmi request notes 1. higher default priority 2. lower default priority remarks 1. values a to c in the above figure are temporary names given to distinguish interrupt requests. 2. the higher/lower default priority indicates relative priority between two interrupt requests. 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. the interrupt control register can be read/written in 8- or 1-bit units. caution if the following three conditions conflict, interrupt servicing is executed twice. however, when dma is not used, interrupt servicing is not executed twice. ? execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) ? an interrupt of the same interrupt control register (xxicn) as the interrupt request flag (xxifn) is generated via hardware ? dma is started during execution of a bit manipulation instruction corresponding to the interrupt request flag (xxifn) two workarounds using software are shown below. ? insert a di instruction before the software-based bit manipulation instruction and an ei instruction after it, so that jumping to an interrupt immediately after the bit manipulation instruction execution does not occur. ? when an interrupt request is acknowledged, since the hardware becomes interrupt disabled (di state), clear the interrupt request flag (xxifn) before executing the ei instruction in each interrupt servicing routine.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 173 after reset: 47h r/w address: fffff100h to fffff156h 76543210 xxicn xxifn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 xxifn interrupt request flag note 0 interrupt request not generated 1 interrupt request generated xxmkn interrupt mask flag 0 interrupt servicing enabled 1 interrupt servicing disabled (pending) xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) note automatically reset by hardware when interrupt request is acknowledged. remark xx: identification name of each peripheral unit (wdt, p, wtni, tm, cs, ser, st, ad, dma, wtn, can, kr) n: peripheral unit number (see table 7-2)
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 174 the addresses and bits of each interrupt control register are as follows. table 7-2. interrupt control registers (xxicn) bit address register 76543210 fffff100h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff102h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff104h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff106h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff108h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff10ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff10ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff10eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff110h csic4 csif4 csmk4 0 0 0 cspr42 cspr41 cspr40 fffff112h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff114h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff116h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff118h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff11ah tmic00 tmif00 tmmk00 0 0 0 tmpr002 tmpr001 tmpr000 fffff11ch tmic01 tmif01 tmmk01 0 0 0 tmpr012 tmpr011 tmpr010 fffff11eh tmic10 tmif10 tmmk10 0 0 0 tmpr102 tmpr101 tmpr100 fffff120h tmic11 tmif11 tmmk11 0 0 0 tmpr112 tmpr111 tmpr110 fffff122h tmic2 tmif2 tmmk2 0 0 0 tmpr22 tmpr21 tmpr20 fffff124h tmic3 tmif3 tmmk3 0 0 0 tmpr32 tmpr31 tmpr30 fffff126h tmic4 tmif4 tmmk4 0 0 0 tmpr42 tmpr41 tmpr40 fffff128h tmic5 tmif5 tmmk5 0 0 0 tmpr52 tmpr51 tmpr50 fffff12ah wtnic wtnif wtnmk 0 0 0 wtnpr2 wtnpr1 wtnpr0 fffff12ch wtniic wtniif wtnimk 0 0 0 wtnipr2 wtnipr1 wtnipr0 fffff12eh csic0 csif0 csmk0 0 0 0 cspr02 cspr01 cspr00 fffff130h seric0 serif0 sermk0 0 0 0 serpr02 serpr01 serpr00 fffff132h csic1 csif1 csmk1 0 0 0 cspr12 cspr11 cspr10 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff138h canic1 canif1 canmk1 0 0 0 canpr12 canpr11 canpr10 fffff13ah canic2 canif2 canmk2 0 0 0 canpr22 canpr21 canpr20 fffff13ch canic3 canif3 canmk3 0 0 0 canpr32 canpr31 canpr30 fffff13eh canic7 canif7 canmk7 0 0 0 canpr72 canpr71 canpr70 fffff140h tmic6 tmif6 tmmk6 0 0 0 tmpr62 tmpr61 tmpr60 fffff142h tmic70 tmif70 tmmk70 0 0 0 tmpr702 tmpr701 tmpr700 fffff144h tmic71 tmif71 tmmk71 0 0 0 tmpr712 tmpr711 tmpr710 fffff146h seric1 serif1 sermk1 0 0 0 serpr12 serpr11 serpr10 fffff148h csic3 csif3 csmk3 0 0 0 cspr32 cspr31 cspr30 fffff14ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff14ch dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff14eh dmaic4 dmaif4 dmamk4 0 0 0 dmapr42 dmapr41 dmapr40 fffff150h dmaic5 dmaif5 dmamk5 0 0 0 dmapr52 dmapr51 dmapr50 fffff152h canic4 note canif4 canmk4 0 0 0 canpr42 canpr41 canpr40 fffff154h canic5 note canif5 canmk5 0 0 0 canpr52 canpr51 canpr50 fffff156h canic6 note canif6 canmk6 0 0 0 canpr62 canpr61 canpr60 note available only for the pd703079y and 70f3079y.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 175 7.3.5 in-service priority register (ispr) this register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset (0) by hardware. however, it is not reset (0) when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8- or 1-bit units. after reset: 00h r address: fffff166h 76543210 ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 isprn indicates priority of interrupt currently acknowledged 0 interrupt request with priority n not acknowledged 1 interrupt request with priority n acknowledged remark n: 0 to 7 (priority level) 7.3.6 interrupt disable flag (id) the interrupt disable flag (id) controls the operating status of maskable interrupt requests and stores the enable/disable control information of interrupt requests. it is allocated in the psw. figure 7-9. interrupt disable flag (id) after reset: 00000020h 31 876543210 psw 0 np ep id sat cy ov s z id specifies maskable interrupt servicing note 0 maskable interrupt acknowledgement enabled 1 maskable interrupt acknowledgement disabled (pending) note interrupt disable flag (id) function it is set (1) by the di instruction and reset (0) by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupts and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request generated during the acknowledgement disabled period (id = 1) can be acknowledged when the xxifn bit of xxicn is set (1), and the id flag is reset (0). remark xx: identification name of each peripheral unit (wdt, p, wtni, tm, cs, ser, st, ad, dma, wtn, can, kr) n: peripheral unit number (see table 7-2)
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 176 7.3.7 watchdog timer mode register (wdtm) this register can be read/written in 8- or 1-bit units (for details, refer to chapter 10 watchdog timer function ). after reset: 00h r/w address: fffff384h 76543210 wdtm run 0 0 wdtm4 0 0 0 0 run watchdog timer operation control 0 count operation stopped 1 count started after clearing wdtm4 timer mode selection/interrupt control by wdt 0 interval timer mode 1 wdt mode caution if the run or wdtm4 bit is set to 1, that bit can only be cleared by reset input. 7.3.8 noise elimination (1) noise elimination of intp0 to intp3 pins the intp0 to intp3 pins incorporate a noise eliminator that functions via analog delay. therefore, a signal input to each pin is not detected as an edge, unless it maintains its input level for a certain period. an edge is detected after a certain period has elapsed. (2) noise elimination of intp4 and intp5 pins the intp4 and intp5 pins incorporate a digital noise eliminator. if an input level of the intp pin is detected by the sampling clock (f xx ) and the same level is not detected three successive times, the input pulse is eliminated as a noise. note the following: ? if the input pulse width is 2 or 3 clocks, whether it is detected as a valid edge or eliminated as a noise is undetermined. to securely detect the valid edge, the same level input of 3 clocks or more is required. ? when noise is generated in synchronization with the sampling clock, this may not be recognized as noise. in this case, eliminate the noise by adding a filter to the input pin.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 177 (3) noise elimination of intp6 pin the intp6 pin incorporates a digital noise eliminator. the sampling clock for digital sampling can be selected from among f xx , f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . sampling is performed 3 times. the noise elimination control register (ncc) selects the clock to be used. remote control signals can be received effectively with this function. f xt can be used for the noise elimination clock. in this case, the intp6 external interrupt function is enabled in the idle/stop mode. this register can be read/written in 8- or 1-bit units. caution after the sampling clock has been changed, it takes 3 sampling clocks to initialize the noise eliminator. for that reason, if an intp6 valid edge was input within these 3 clocks, an interrupt request may occur. therefore, observe the following points when using the interrupt and dma functions. ? ? ? ? when using the interrupt function, after 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (bit 7 of pic6) has been cleared. ? ? ? ? when using the dma function, after 3 sampling clocks have elapsed, enable dma by setting bit 0 of dchcn. after reset: 00h r/w address: fffff3d4h 7 6543210 ncc 00 000 ncs2 ncs1 ncs0 reliably eliminated noise width note ncs2 ncs1 ncs0 sampling clock f xx = 16 mhz f xx = 8 mhz 000 f xx 125.0 ns 250.0 ns 001 f xx /64 8.0 s 16.0 s 010 f xx /128 16.0 s 32.0 s 011 f xx /256 32.0 s 64.0 s 100 f xx /512 64.0 s 128.0 s 101 f xx /1024 128.0 s 256.0 s 110 setting prohibited 111 f xt 61 s note since sampling is preformed three times, the reliably eliminated noise width is 2 noise elimination clock.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 178 7.3.9 edge detection function the valid edges of the intp0 to intp6 pins can be selected for each pin from the following four types. ? rising edge ? falling edge ? both rising and falling edges ? neither rising nor falling edge detected the validity of the rising edge is controlled by rising edge specification register 0 (egp0), and the validity of the falling edge is controlled by falling edge specification register 0 (egn0). refer to 7.2.5 edge detection function of nmi pin for details of egp0 and egn0. after reset, the valid edge of the nmi pin is set to the ?neither rising nor falling edge detected? state. therefore, the nmi pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the egp0 and egn0 registers. when using p01 to p07 as output ports, set the valid edges of intp0 to intp6 to ?neither rising nor falling edge detected? or mask the interrupt request.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 179 7.4 software exception a software exception is generated when the cpu executes the trap instruction, and can always be acknowledged. ? trap instruction format: trap vector (where vector is 0 to 1fh) for details of the instruction function, refer to the v850 family user?s manual architecture. 7.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of the psw. (5) loads the handler address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. how a software exception is processed is shown below. figure 7-10. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing handler address: 00000040h (vector = 0nh) 00000050h (vector = 1nh)
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 180 7.4.2 restore to restore or return execution from the software exception service routine, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-11. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoration by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 181 7.4.3 ep flag the ep flag in the psw is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs, and disables interrupts. figure 7-12. ep flag (ep) after reset: 00000020h 31 876543210 psw 0 np ep id sat cy ov s z ep exception processing 0 exception processing is not in progress 1 exception processing is in progress 7.5 exception trap the exception trap is an interrupt that is requested when illegal execution of an instruction takes place. in the v850/sf1, an illegal op code exception (ilgop: ilegal opcode trap) is considered as an exception trap. ? illegal op code exception: occurs if the sub op code field of an instruction to be executed next is not a valid op code. 7.5.1 illegal op code definition an illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111b and bits 23 to 26 being 0011b to 1111b. figure 7-13. illegal op code 15 16 17 23 22 x 21 x 20 xxxxx x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 x : don?t care 7.5.2 operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code (0060h) to the lower 16 bits (eicc) of ecr. (4) sets the ep and id bits of the psw. (5) loads the handler address (00000060h) for the exception trap routine to the pc, and transfers control.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 182 how the exception trap is processed is shown below. figure 7-14. exception trap processing exception trap (ilgop) occurs eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 00000060h cpu processing exception processing 7.5.3 restore to restore or return execution from the exception trap, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 183 the processing of the reti instruction is shown below. figure 7-15. reti instruction processing reti instruction jump to pc pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during exception trap processing, in order to restore the pc and psw correctly during restoration by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 184 7.6 priority control 7.6.1 priorities of interrupts and exceptions table 7-3. priorities of interrupts and exceptions reset nmi int trap ilgop reset * * * * nmi int trap ilgop reset: reset nmi: non-maskable interrupt int: maskable interrupt trap: software exception ilgop: illegal op code exception *: the item on the left ignores the item above. : the item on the left is ignored by the item above. : the item above is higher than the item on the left in priority. : the item on the left is higher than the item above in priority. 7.6.2 multiple interrupt servicing multiple interrupt servicing is a function that allows the nesting of interrupts. if a higher priority interrupt is generated and acknowledged, it will be allowed to stop the interrupt service routine currently in progress. execution of the original routine will resume once the higher priority interrupt routine is completed. if an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. multiple interrupt servicing control is performed when interrupts are enabled (id = 0). even in an interrupt servicing routine, multiple interrupt control must be performed when interrupts are enabled (id = 0). if a maskable interrupt or exception is generated during the service program of maskable interrupt or exception, eipc and eipsw must be saved. the following example shows the procedure of interrupt nesting.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 185 (1) to acknowledge maskable interrupts in service program service program of maskable interrupt or exception (2) to generate exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgement) ... ... ? di instruction (disables interrupt acknowledgement) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgement) ... ? trap instruction ? illegal op code ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction acknowledges interrupt such as intp input. acknowledges exception such as trap instruction. acknowledges exception such as illegal op code.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 186 priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. to set a priority level, write values to the xxprn0 to xxprn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt request. at reset, the interrupt request is masked by the xxmkn bit, and the priority level is set to 7 by the xxprn0 to xxprn2 bits. remark xx: identification name of each peripheral unit (wdt, p, wtni, tm, cs, ser, st, ad, dma, wtn, can, kr) n: peripheral unit number (see table 7-2) priorities of maskable interrupts (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routine (time until the reti instruction is executed), maskable interrupts are held pending without being acknowledged.
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 187 7.7 response time the following table describes the interrupt response time (from interrupt request generation to start of interrupt servicing). figure 7-16. pipeline operation at interrupt request acknowledgement system clock if id ifx idx ifx ex mem int1 int2 int3 if id ex mem wb int4 wb interrupt request instruction 1 instruction 2 instruction 3 interrupt acknowledge operation instruction (start instruction of interrupt servcing routine) 7 to 14 system clocks 4 system clocks int1 to int4: interrupt acknowledge processing if x : invalid instruction fetch id x : invalid instruction decode interrupt response time (system clock) internal interrupt external interrupt conditions minimum 11 13 maximum 18 20 time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: ? in idle/stop mode ? external bus is accessed ? two or more interrupt request non-sample instructions are executed in succession ? accessing interrupt control register 7.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. interrupt request non-sample instruction ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (vs. psw)
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 188 (1) acknowledgement of interrupt servicing following ei instruction the v850/sf1 requires a minimum of 7 clocks from the occurrence of an interrupt request until the interrupt request is acknowledged as the interrupt request determination period. since instructions can continue to be executed during this period, executing the di (disable interrupt) instruction results in the interrupt disabled state. as a result, all interrupt requests are held pending until the ei (enable interrupt) instruction is executed. moreover, since an interrupt determination period is also required when the ei instruction is executed, at least 7 clocks are required between execution of the ei instruction and acknowledgement of the interrupt request. therefore, if the di instruction is executed before 7 clocks have elapsed following execution of the ei instruction, interrupts will be held pending. to reliably acknowledge interrupts, insert instructions whose execution clocks total 7 clocks or more between the ei instruction and di instruction. this does not apply, however, to the following instructions. ? idle/stop mode setting ? ei instruction, di instruction ? reti instruction ? ldsr instruction (for psw register) ? access to interrupt control register (xxlcn) example: when ei instruction servicing is not enabled [program example] di ;mk flag = 0 (interrupt request enable) ; interrupt request occurrence ( if flag = 1 ) ei jr lp1 ;7 clocks have not elapsed between ei instruction and di instruction ( 3 clocks) lp1: di ; interrupt request not acknowledged
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 189 [workaround program example] di ;mk flag = 0 (interrupt request enable) ; interrupt request occurrence ( if flag = 1 ) ei nop ;1 system clock nop ;1 system clock nop ;1 system clock nop ;1 system clock jr lp1 ;3 system clocks (branching to lp1 routine) lp1: di ; interrupt servicing executed at 8 th system clock following execution of ei instruction
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 190 7.9 key interrupt function a key interrupt can be generated by inputting a falling edge to the key input pins (kr0 to kr7) by setting the key return mode register (krm). the key return mode register (krm) includes 5 bits. the krm0 bit controls the kr0 to kr3 signals in 4-bit units and the krm4 to krm7 bits control corresponding signals from kr4 to kr7 (arbitrary setting from 4 to 8 bits is possible). this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff3d0h 76543210 krm krm7 krm6 krm5 krm4 0 0 0 krm0 krmn key return mode control 0 key return signal not detected 1 key return signal detected caution if the key return mode register (krm) is changed, an interrupt request flag may be set. to avoid this flag being set, change the krm register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag. table 7-4. description of key return detection pin flag pin description krm0 controls kr0 to kr3 signals in 4-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units
chapter 7 interrupt/exception processing function user?s manual u14665ej2v0um 191 figure 7-17. key return block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 000 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
192 user?s manual u14665ej2v0um chapter 8 timer/counter function 8.1 16-bit timer (tm0, tm1, tm7) remark n = 0, 1, 7 in section 8.1. 8.1.1 outline ? 16-bit capture/compare registers: 2 (crn0, crn1) ? independent capture/trigger inputs: 2 (tin0, tin1) ? support of output of capture/match interrupt request signals (inttmn0, inttmn1) ? event input (shared with tin0) via digital noise eliminator and support of edge specifications ? timer output operated by match detection: 1 each (ton) when using the p104/to0, p107/to1, and p100/to7 pins as to0, to1, and to7 (timer output), set the value of port 10 (p10) to 0 (port mode output) and the port 10 mode register (pm10) to 0. the logical sum (ored) value of the output of a port and a timer is output. 8.1.2 function tm0, tm1, and tm7 have the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square wave output ? one-shot pulse output figure 8-1 shows the block diagram.
chapter 8 timer/counter function user?s manual u14665ej2v0um 193 figure 8-1. block diagram of tm0, tm1, and tm7 internal bus internal bus tin1 noise eliminator count clock note tin0 toen tocn1 lvrn lvsn tocn4 ospen osptn ovfn tmcn1 tmcn2 prescaler mode register n0 (prmn0) prmn1 prmn0 tmcn3 crcn0 crcn1 crcn2 capture/compare control register n (crcn) 16-bit capture/compare register n0 (crn0) output controller 16-bit timer register (tmn) 16-bit capture/compare register n1 (crn1) crcn2 match match clear 16-bit timer mode control register n (tmcn) ton inttmn1 inttmn0 3 timer output control register n (tocn) f xx /2 selector selector selector selector prmn2 prescaler mode register n1 (prmn1) noise eliminator noise eliminator note the count clock is set by the prmn0 and prmn1 registers. (1) interval timer generates an interrupt at preset time intervals. (2) ppg output can output a square wave with a frequency and output-pulse width that can be set arbitrarily. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counter can measure the number of pulses of a signal input from an external source.
chapter 8 timer/counter function 194 user?s manual u14665ej2v0um (5) square wave output can output a square wave of any frequency. (6) one-shot pulse output can output a one-shot pulse with any output pulse width. 8.1.3 configuration timers 0, 1, and 7 include the following hardware. table 8-1. configuration of timers 0, 1, and 7 item configuration timer registers 16 bits 3 (tm0, tm1, tm7) registers capture/compare registers: 16 bits 6 (crn0, crn1) timer outputs 3 (to0, to1, to7) control registers 16-bit timer mode control register n (tmcn) capture/compare control register n (crcn) 16-bit timer output control register n (tocn) prescaler mode registers n0, n1 (prmn0, prmn1) (1) 16-bit timer registers 0, 1, 7 (tm0, tm1, tm7) tmn is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> at reset input <2> if tmcn3 and tmcn2 are cleared <3> if the valid edge of tin0 is input in the clear & start mode set by inputting the valid edge of tin0 <4> if tmn and crn0 match in the clear & start mode set on a match between tmn and crn0 <5> if osptn is set or if the valid edge of tin0 is input in the one-shot pulse output mode
chapter 8 timer/counter function user?s manual u14665ej2v0um 195 (2) capture/compare register n0 (cr00, cr10, cr70) crn0 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by bit 0 (crcn0) of the crcn register. (a) when using crn0 as compare register the value set to crn0 is always compared with the count value of the tmn register. when the values of the two match, an interrupt request (inttmn0) is generated. when tmn is used as an interval timer, crn0 can also be used as a register that holds the interval time. (b) when using crn0 as capture register the valid edge of the tin0 or tin1 pin can be selected as a capture trigger. the valid edge for tin0 or tin1 is set by using the prmn0 register. when the valid edge for tin0 pin is specified as the capture trigger, refer to table 8-2 . when the valid edge for tin1 pin is specified as the capture trigger, refer to table 8-3 . table 8-2. valid edge of tin0 pin and capture trigger of crn0 esn01 esn00 valid edge of tin0 pin crn0 capture trigger 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation table 8-3. valid edge of tin1 pin and capture trigger of crn0 esn11 esn10 valid edge of tin1 pin crn0 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges crn0 is set by a 16-bit memory manipulation instruction. reset input makes this register undefined. caution in the clear & start mode entered on a match between tmn and crn0, set a value other than 0000h to crn0. in the free running mode or the tin0 valid edge clear mode, however, an interrupt request (inttmn0) is generated after an overflow (ffffh) when 0000h is set to crn0.
chapter 8 timer/counter function 196 user?s manual u14665ej2v0um (3) capture/compare register n1 (cr01, cr11, cr71) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 (crcn2) of the crcn register. (a) when using crn1 as compare register the value set to crn1 is always compared with the count value of tmn. when the values of the two match, an interrupt request (inttmn1) is generated. (b) when using crn1 as capture register the valid edge of the tin1 pin can be selected as a capture trigger. the valid edge of tin1 is specified using the prmn0 register. when the capture trigger is specified as the valid edge of tin0, the relationship between the tin0 valid edge and the crn1 capture trigger is as follows. table 8-4. tin0 pin valid edge and crn1 capture trigger esn01 esn00 tin0 pin valid edge crn1 capture trigger 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges crn1 is set by a 16-bit memory manipulation instruction. reset input makes this register undefined. caution in the clear & start mode entered on a match between tmn and crn0, set a value other than 0000h to crn1. in the free running mode or the tin1 valid edge clear mode, however, an interrupt request (inttmn1) is generated after an overflow (ffffh) when 0000h is set to crn1.
chapter 8 timer/counter function user?s manual u14665ej2v0um 197 8.1.4 timer 0, 1, 7 control registers the registers to control timers 0, 1, 7 are shown below. ? 16-bit timer mode control register n (tmcn) ? capture/compare control register n (crcn) ? 16-bit timer output control register n (tocn) ? prescaler mode registers n0, n1 (prmn0, prmn1) (1) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn specifies the operation mode of the 16-bit timer, and the clear mode, output timing, and overflow detection of the 16-bit timer register n. tmcn is set by an 8- or 1-bit memory manipulation instruction. reset input clears tmc0, tmc1, and tmc7 to 00h. caution 16-bit timer register n starts operating when a value other than 0, 0 (operation stop mode) is set to tmcn2 and tmcn3. to stop the operation, set 0, 0 to tmcn2 and tmcn3.
chapter 8 timer/counter function 198 user?s manual u14665ej2v0um after reset: 00h r/w address: fffff208h, fffff218h, fffff3a8h 76543210 tmcn 0 0 0 0 tmcn3 tmcn2 tmcn1 ovfn tmcn3 tmcn2 tmcn1 selects operation mode and clear mode selects ton output timing generation of interrupt 0 0 0 operation stops (tmn is cleared to 0) not affected not generated 001 0 1 0 free running mode match between tmn and crn0 or match between tmn and crn1 0 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 0 0 clears and starts at valid edge of tin0 match between tmn and crn0 or match between tmn and crn1 1 0 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 1 1 0 clears and starts on match between tmn and crn0 match between tmn and crn0 or match between tmn and crn1 1 1 1 match between tmn and crn0, match between tmn and crn1, or valid edge of tin0 ovfn detection of overflow of 16-bit timer register n 0 did not overflow 1 overflow occurred generated on match between tmn and crn0 and match between tmn and crn1
chapter 8 timer/counter function user?s manual u14665ej2v0um 199 cautions 1. when a bit other than the ovfn flag is written, be sure to stop the timer operation. 2. the valid edge of the tin0 pin is set by using prescaler mode register n0 (prmn0). 3. when a mode in which the timer is cleared and started on a match between tmn and crn0 is selected, the ovfn flag is set to 1 when the count value of tmn changes from ffffh to 0000h with crn0 set to ffffh. remark ton: output pin of timer n tin0: input pin of timer n tmn: 16-bit timer register n crn0: compare register n0 crn1: compare register n1
chapter 8 timer/counter function 200 user?s manual u14665ej2v0um (2) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn controls the operation of capture/compare register n (crn0 and crn1). crcn is set by an 8- or 1-bit memory manipulation instruction. reset input clears crc0, crc1, and crc7 to 00h. after reset: 00h r/w address: fffff20ah, fffff21ah, fffff3aah 76543210 crcn 0 0 0 0 0 crcn2 crcn1 crcn0 crcn2 selects operation mode of crn1 0 operates as compare register 1 operates as capture register crcn1 selects capture trigger of crn0 0 captured at valid edge of tin1 1 captured in reverse phase of valid edge of tin0 crcn0 selects operation mode of crn0 0 operates as compare register 1 operates as capture register cautions 1. before setting crcn, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on a match between tmn and crn0 is selected by 16-bit timer mode control register n (tmcn), do not specify crn0 as a capture register. 3. when both the rising edge and falling edge are specified for the tin0 valid edge, the capture operation does not work. 4. for the capture trigger, a pulse longer than twice the count clock selected by prescaler mode registers 0n, 1n (prm0n, prm1n) is required for the signals from tin0 and t2n1 to perform the capture operation correctly.
chapter 8 timer/counter function user?s manual u14665ej2v0um 201 (3) 16-bit timer output control registers 0, 1, 7 (toc0, toc1, toc7) tocn controls the operation of the timer n output controller by setting or resetting the r-s flip-flop (lv0), enabling or disabling inverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. tocn is set by an 8- or 1-bit memory manipulation instruction. reset input clears toc0, toc1, and toc7 to 00h.
chapter 8 timer/counter function 202 user?s manual u14665ej2v0um after reset: 00h r/w address: fffff20ch, fffff21ch, fffff3ach 76543210 tocn 0 osptn ospen tocn4 lvsn lvrn tocn1 toen osptn controls output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 one-shot pulse trigger used ospen controls one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output note tocn4 controls timer output f/f on match between crn1 and tmn 0 inverse timer output f/f disabled 1 inverse timer output f/f enabled lvsn lvrn sets status of timer output f/f of timer 0 0 0 not affected 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tocn1 controls timer output f/f on match between crn0 and tmn 0 inverse timer output f/f disabled 1 inverse timer output f/f enabled toen controls output of timer n 0 output disabled (output is fixed to 0 level) 1 output enabled note the one-shot pulse output operates only in the free-running mode and in the clear & start mode entered upon detection of tin0 valid edge. cautions 1. before setting tocn, be sure to stop the timer operation. 2. lvsn and lvrn are 0 when read after data has been set to them. 3. osptn is 0 when read because it is automatically cleared after data has been set. 4. do not set osptn (to 1) for other than one-shot pulse output.
chapter 8 timer/counter function user?s manual u14665ej2v0um 203 (4) prescaler mode registers 00, 01 (prm00, prm01) prm00 and prm01 select the count clock of the 16-bit timer (tm0) and the valid edge of ti00 or ti01 input. prm00 and prm01 are set by an 8-bit memory manipulation instruction. reset input clears prm00 and prm01 to 00h. after reset: 00h r/w address: fffff206h 76543210 prm00 es011 es010 es001 es000 0 0 prm01 prm00 after reset: 00h r/w address: fffff20eh 76543210 prm010000000prm02 es011 es010 selects valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es001 es000 selects valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prm02 prm01 prm00 count clock 16 mhz 8 mhz 000f xx /2 125 ns 250 ns 001f xx /16 1 s2 s 0 1 0 intwtni ?? 0 1 1 ti00 valid edge note ?? 100f xx /4 250 ns 500 ns 101f xx /64 4 s8 s 110f xx /256 16 s 32 s 1 1 1 setting prohibited ?? note an external clock requires a pulse longer than twice the internal clock (f xx /2).
chapter 8 timer/counter function 204 user?s manual u14665ej2v0um cautions 1. when selecting the valid edge of ti00 or ti01 as the count clock, do not specify the valid edge of ti00 or ti01 to clear and start the timer and as a capture trigger. 2. before setting data to prm00 and prm01, always stop the timer operation. 3. if the 16-bit timer (tm0) operation is enabled by specifying the rising edge or both edges as the valid edge of the ti00 or ti01 pin while the ti00 or ti01 pin is high level immediately after system reset, the rising edge is detected immediately after specification of the rising edge or both edges. care is therefore needed when pulling up the ti00 or ti01 pin. however, the rising edge is not detected when operation is enabled after it has been stopped.
chapter 8 timer/counter function user?s manual u14665ej2v0um 205 (5) prescaler mode registers m0, m1 (prmm0, prmm1) prmm0 and prmm1 select the count clock of the 16-bit timer (tm1, tm7) and the valid edge of the tim0, tim1 input. prmm0 and prmm1 are set by an 8-bit memory manipulation instruction (m = 1, 7). reset input clears prmm0 and prmm1 to 00h. after reset: 00h r/w address: fffff216h, fffff3a6h 76543210 prmm0 esm11 esm10 esm01 esm00 0 0 prmm1 prmm0 after reset: 00h r/w address: fffff21eh, fffff3aeh 76543210 prmm10000000prmm2 esm11 esm10 selects valid edge of tim1 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges esm01 esm00 selects valid edge of tim0 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges count clock selection f xx prmm2 prmm1 prmm0 count clock 16 mhz 8 mhz 000f xx /2 125 ns 250 ns 001f xx /4 250 ns 500 ns 010f xx /16 1 s2 s 0 1 1 tim0 valid edge note ?? 100f xx /32 2 s4 s 101f xx /128 8 s 16 s 110f xx /256 16 s 32 s 1 1 1 setting prohibited ?? note an external clock requires a pulse longer than twice the internal clock (f xx /2).
chapter 8 timer/counter function 206 user?s manual u14665ej2v0um cautions 1. when selecting the valid edge of tim0, tim1 as the count clock, do not specify the valid edge of tim0, tim1 to clear and start the timer and as a capture trigger. 2. before setting data to prmm0, prmm1, always stop the timer operation. 3. if the 16-bit timer (tm1, tm7) operation is enabled by specifying the rising edge or both edges for the valid edge of the tim0, tim1 pin while the tim0, tim1 pin is high level immediately after system reset, the rising edge is detected immediately after specification of the rising edge or both edges. care is therefore needed when pulling up the tim0, tim1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped. remark m = 1, 7
chapter 8 timer/counter function user?s manual u14665ej2v0um 207 8.2 16-bit timer (tm0, tm1, tm7) operation remark n = 0, 1, 7 in section 8.2. 8.2.1 operation as interval timer tmn operates as an interval timer when 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) are set as shown in figure 8-2. in this case, tmn repeatedly generates an interrupt at the time interval specified by the count value preset to 16- bit capture/compare register n (crn0). when the count value of tmn matches the set value of crn0, the value of tmn is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttmn0) is generated. the count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (prmn0 and prmn1) of prescaler mode register n0 (prmn0) and by bits 0 (prmn2) of prescaler mode register n1 (prmn1). figure 8-2. control register settings when tmn operates as interval timer (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the interval timer function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function 208 user?s manual u14665ej2v0um figure 8-3. configuration of interval timer note the count clock is set by the prmn0 and prmn1 registers. remark ? ? indicates a signal that can be directly connected to ports. figure 8-4. timing of interval timer operation tmn count value crn0 0000h 0001h n n n n n n n 0000h 0001h 0000h 0001h count start clear clear interrupt acknowledgement interrupt acknowledgement inttmn0 ton interval time interval time interval time count clock t remark interval time = (n + 1) t: n = 0001h to ffffh tin0 noise eliminator 16-bit capture/compare register n0 (crn0) count clock note selector 16-bit timer register n (tmn) ovfn clear circuit inttmn0 f xx /2
chapter 8 timer/counter function user?s manual u14665ej2v0um 209 8.2.2 ppg output operation tmn can be used for ppg (programmable pulse generator) output by setting 16-bit timer mode control register n (tmcn) and capture/compare control register n (crcn) as shown in figure 8-5. the ppg output function outputs a square wave from the ton pin with a cycle specified by the count value preset to 16-bit capture/compare register n0 (crn0) and a pulse width specified by the count value preset to 16-bit capture/compare register n1 (crn1). figure 8-5. control register settings in ppg output operation (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 (toc0, toc1, toc7) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00010/10/111 enables ton output. reverses output on match between tmn and crn0. specifies initial value of ton output f/f. reverses output on match between tmn and crn1. disables one-shot pulse output. cautions 1. make sure that crn0 and crn1 are set to 0000h < crn1 < crn0 ffffh. 2. ppg output sets the pulse cycle to (crn0 setup value + 1). the duty factor is (crn1 setup value + 1)/(crn0 setup value + 1). : don?t care
chapter 8 timer/counter function 210 user?s manual u14665ej2v0um 8.2.3 pulse width measurement 16-bit timer register n (tmn) can be used to measure the pulse widths of the signals input to the tin0 and tin1 pins. measurement can be carried out with tmn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the tin0 pin. (1) pulse width measurement with free-running counter and one capture register if the edge specified by prescaler mode register n0 (prmn0) is input to the tin0 pin when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-6 ), the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the edge is specified using bits 6 and 7 (esn10 and esn11) of prescaler mode register n0 (prmn0). the rising edge, falling edge, or both edges can be selected. the valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. figure 8-6. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 1 0/1 0 crn0 as compare register crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function user?s manual u14665ej2v0um 211 figure 8-7. configuration for pulse width measurement with free-running counter note the count clock is set by the prmn0 and prmn1 registers. remark ? ? indicates a signal that can be directly connected to ports. figure 8-8. timing of pulse width measurement with free-running counter and one capture register (with both edges specified) 16-bit capture/compare register n1 (crn1) 16-bit timer register n (tmn) internal bus count clock note tin0 selector ovfn inttmn1 t 0000h 0000h ffffh 0001h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t count clock tmn count value tin0 pin input value loaded to crn1 inttmn1 ovfn
chapter 8 timer/counter function 212 user?s manual u14665ej2v0um (2) measurement of two pulse widths with free-running counter the pulse widths of the two signals respectively input to the tin0 and tin1 pins can be measured when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-9 ). when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1) and an external interrupt request signal (inttmn1) is set. when the edge specified by bits 6 and 7 (esn10 and esn11) of prmn0 is input to the tin1 pin, the value of tmn is loaded to 16-bit capture/compare register n0 (crn0), and an external interrupt request signal (inttmn0) is set. the edges of the tin0 and tin1 pins are specified by bits 4 and 5 (esn00 and esn01) and bits 6 and 7 (esn10 and esn11) of prmn0, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. figure 8-9. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn00000101 crn0 as capture register captures valid edge of tin1 pin to crn0. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function user?s manual u14665ej2v0um 213 ? capture operation (free-running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 8-10. crn1 capture operation with rising edge specified count clock tmn tin0 crn1 inttmn1 n + 1 n n ? 1 n ? 2 n ? 3 n rising edge detection figure 8-11. timing of pulse width measurement with free-running counter (with both edges specified) t value loaded to crn1 (d1 ? d0) t (10000h ? d1 + d2) t(d3 ? d2) t (10000h ? d1 + (d2 + 1) t 0000h 0001h d0 count clock tmn count value tin0 pin input inttmn1 tin1 pin input inttmn0 ovfn value loaded to crn0 d0+1 d1 d1+1 ffffh 0000h d2 d2+1 d2+2 d3 d0 d1 d2 d1 d2+1
chapter 8 timer/counter function 214 user?s manual u14665ej2v0um (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer register n (tmn) is used as a free-running counter (refer to figure 8-12 ), the pulse width of the signal input to the tin0 pin can be measured. when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0) is input to the tin0 pin, the value of tmn is loaded to 16-bit capture/compare register n1 (crn1), and an external interrupt request signal (inttmn1) is set. the value of tmn is also loaded to 16-bit capture/compare register n0 (crn0) when an edge that is the reverse of the one that triggers capturing to crn1 is input. the edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising or falling edge can be specified. the valid edge of tin0 is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (prmn0, prmn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform a capture operation. figure 8-12. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000010/10 free-running mode (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn00000111 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0 pin. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function user?s manual u14665ej2v0um 215 figure 8-13. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) t ( d1 ? d0 ) t ( 10000h ? d1 + d2 ) t ( d3 ? d2 ) t ovfn 0001h 0000h d0 d1 count clock tmn count value tin0 pin input inttmn1 value loaded to crn1 value loaded to crn0 d0+1 d1+1 0000h ffffh d2 d2+1 d3 d0 d1 d2 d3 (4) pulse width measurement by restarting when the valid edge of the tin0 pin is detected, the pulse width of the signal input to the tin0 pin can be measured by clearing 16-bit timer register n (tmn) once and then resuming counting after loading the count value of tmn to 16-bit capture/compare register n1 (crn1). (see figure 8-15 ) the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising or falling edge can be specified. the valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (prmn0, prmn1) and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. caution if the valid edge of the tin0 pin is specified to be both the rising and falling edges, capture/compare register n0 (crn0) cannot perform a capture operation.
chapter 8 timer/counter function 216 user?s manual u14665ej2v0um figure 8-14. control register settings for pulse width measurement by restarting (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000100/10 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn00000111 crn0 as capture register captures to crn0 at edge reverse to valid edge of tin0. crn1 as capture register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. for details, refer to 8.1.4 timer 0, 1, 7 control registers . figure 8-15. timing of pulse width measurement by restarting (with rising edge specified) t (d1 + 1) t (d2 + 1) t 0001h 0000h d0 d2 d1 count clock tmn count value tin0 pin input inttmn1 d0 d2 value loaded to crn1 value loaded to crn0 d1 0001h 0000h 0001h 0000h
chapter 8 timer/counter function user?s manual u14665ej2v0um 217 8.2.4 operation as external event counter tmn can be used as an external event counter that counts the number of clock pulses input to the tin0 pin from an external source by using 16-bit timer register n (tmn). each time the valid edge specified by prescaler mode register n0 (prmn0) has been input, tmn is incremented. when the count value of tmn matches the value of 16-bit capture/compare register n0 (crn0), tmn is cleared to 0, and an interrupt request signal (inttmn0) is generated. the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected by sampling with a count clock cycle of f xx /2, and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. figure 8-16. control register settings in external event counter mode (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn0000110/10 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function 218 user?s manual u14665ej2v0um figure 8-17. configuration of external event counter internal bus 16-bit capture/compare register n0 (crn0) 16-bit timer/counter n (tmn) ovfn count clock note selector inttmn0 16-bit capture/compare register n1 (crn1) noise eliminator valid edge of tin0 f xx /2 match clear note the count clock is set by the prmn0 and prmn1 registers. remark ? ? indicates a signal that can be directly connected to ports. figure 8-18. timing of external event counter operation (with rising edge specified) tin0 pin input tmn count value crn0 inttmn0 0001h 0000h n-1 n n 0003h 0002h 0005h 0004h 0001h 0000h 0003h 0002h caution read tmn when reading the count value of the external event counter. 8.2.5 operation as square-wave output tmn can be used to output a square wave with any frequency at an interval specified by the count value preset to 16-bit capture/compare register n0 (crn0). by setting bits 0 (toen) and 1 (tocn1) of 16-bit timer output control register n (tocn) to 1, the output status of the ton pin is reversed at an interval specified by the count value preset to crn1. in this way, a square wave of any frequency can be output.
chapter 8 timer/counter function user?s manual u14665ej2v0um 219 figure 8-19. control register settings in square-wave output mode (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn00001100 clears and starts on match between tmn and crn0. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0/1 0/1 0 crn0 as compare register (c) 16-bit timer output control registers 0, 1, 7 (toc0, toc1, toc7) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00000/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. does not invert output on match between tmn and crn1. disables one-shot pulse output. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function 220 user?s manual u14665ej2v0um figure 8-20. timing of square-wave output operation count clock tmn count value crn0 inttmn0 0002h 0001h 0000h n-1 n n n-1 n ton pin output 0002h 0001h 0000h 0000h 8.2.6 operation as one-shot pulse output tmn can output a one-shot pulse in synchronization with a software trigger and an external trigger (tin0 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 8-21, and by setting bit 6 (osptn) of tocn by software. by setting osptn to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted at the count value (n) preset to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted at the count value (m) preset to 16-bit capture/compare register n0 (crn0) note . even after a one-shot pulse has been output, tmn continues its operation. to stop tmn, tmcn must be reset to 00h. note this is an example when n < m. when n > m, the output becomes active at the crn0 value and inactive at the crn1 value. caution do not set osptn to 1 while a one-shot pulse is being output. to output a one-shot pulse again, wait until the current one-shot pulse output ends.
chapter 8 timer/counter function user?s manual u14665ej2v0um 221 figure 8-21. control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn00000100 free-running mode (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn0000000/10 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 (toc0, toc1, toc7) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. inverts output on match between tmn and crn1. sets one-shot pulse output mode. set to 1 for output. caution do not set crn0 and crn1 to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function 222 user?s manual u14665ej2v0um figure 8-22. timing of one-shot pulse output operation with software trigger count clock tmn count value 0000h 0001h 0000h n+1 n m+2 n-1 m-1 m+1 n m crn1 set value n crn0 set value m osptn inttmn1 inttmn0 ton pin output sets 0ch to tmcn (tmn count starts) n m n m n m caution 16-bit timer register n starts operating as soon as a value other than 0, 0 (operation stop mode) is set to tmcn2 and tmcn3. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the ton pin by setting 16-bit timer mode control register n (tmcn), capture/compare control register n (crcn), and 16-bit timer output control register n (tocn) as shown in figure 8-23, and by using the valid edge of the tin0 pin as an external trigger. the valid edge of the tin0 pin is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the tin0 pin is detected, the 16-bit timer/event counter is cleared and started, and the output is asserted at the count value (n) preset to 16-bit capture/compare register n1 (crn1). after that, the output is deasserted at the count value (m) preset to 16-bit capture/compare register n0 (crn0) note . note this is an example when n < m. when n > m, the output becomes active at the crn0 value and inactive at the crn1 value. caution even if the external trigger is generated again while a one-shot pulse is being output, it is ignored.
chapter 8 timer/counter function user?s manual u14665ej2v0um 223 figure 8-23. control register settings for one-shot pulse output with external trigger (a) 16-bit timer mode control registers 0, 1, 7 (tmc0, tmc1, tmc7) tmcn3 tmcn2 tmcn1 ovfn tmcn00001000 clears and starts at valid edge of tin0 pin. (b) capture/compare control registers 0, 1, 7 (crc0, crc1, crc7) crcn2 crcn1 crcn0 crcn 0 0 0 0 0 0 0/1 0 crn0 as compare register crn1 as compare register (c) 16-bit timer output control registers 0, 1, 7 (toc0, toc1, toc7) osptn ospen tocn4 lvsn lvrn tocn1 toen tocn00110/10/111 enables ton output. inverts output on match between tmn and crn0. specifies initial value of ton output f/f. inverts output on match between tmn and crn1. sets one-shot pulse output mode. caution do not set crn0 and crn1 to 0000h. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. for details, refer to 8.1.4 timer 0, 1, 7 control registers .
chapter 8 timer/counter function 224 user?s manual u14665ej2v0um figure 8-24. timing of one-shot pulse output operation with external trigger (with rising edge specified) count clock tmn count value 0000h 0001h n+1 m+2 n+2 m-1 m+1 m value to set crn1 n value to set crn0 m tin0 pin input inttmn1 inttmn0 ton pin output sets 08h to tmcn (tmn count starts) 0000h n m-2 n m n m n m caution the 16-bit timer register starts operating as soon as a value other than 0, 0 (operation stop mode) is set to tmcn2 and tmcn3.
chapter 8 timer/counter function user?s manual u14665ej2v0um 225 8.2.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit timer register n (tmn) is started asynchronously to the count pulse. figure 8-25. start timing of 16-bit timer register n (2) 16-bit capture/compare register setting (in the clear & start mode entered on match between tmn and crn0) set 16-bit capture/compare registers n0, n1 (crn0, crn1) to a value other than 0000h (a 1-pulse count operation is disabled when these registers are used as event counters). (3) setting compare register during timer count operation if the value to which the current value of 16-bit capture/compare register n0 (crn0) has been changed is less than the value of 16-bit timer register n (tmn), tmn continues counting, overflows, and starts counting again from 0. if the new value of crn0 (m) is less than the old value (n), the timer must be restarted after the value of crn0 has been changed. figure 8-26. timing after changing compare register during timer count operation tmn count value ffffh 0001h 0002h 0000h count pulse x-1 n m crn0 x remark n > x > m count pulse tmn count value 0004h 0003h 0002h 0001h 0000h timer starts
chapter 8 timer/counter function 226 user?s manual u14665ej2v0um (4) data hold timing of capture register if the valid edge is input to the tin0 pin while 16-bit capture/compare register n1 (crn1) is read, crn1 performs a capture operation, but this capture value is not guaranteed. however, the interrupt request signal (inttmn1) is set as a result of detection of the valid edge. figure 8-27. data hold timing of capture register tmn count value count pulse n + 1 nn + 2 m + 2 m + 1 m x n + 1 capture operation is performed but it is not guaranteed. edge input inttmn1 capture read signal crn1 interrupt value capture operation (5) setting valid edge before setting the valid edge of the tin0 pin, stop the timer operation by resetting bits 2 and 3 (tmcn2 and tmcn3) of 16-bit timer mode control register n to 0, 0. set the valid edge by using bits 4 and 5 (esn00 and esn01) of prescaler mode register n0 (prmn0). (6) re-triggering one-shot pulse (a) one-shot pulse output via software when a one-shot pulse is output, do not set osptn to 1. do not output the one-shot pulse again until the current one-shot pulse output ends. (b) one-shot pulse output via external trigger even if the external trigger is generated again while a one-shot pulse is being output, it is ignored. (c) one-shot pulse output function when using a software trigger for one-shot pulse output of timers 0, 1, and 7, the level of the tin0 pin or its alternate-function pin cannot be changed. the reason for this is that the timer is inadvertently cleared and started at the level of the tin0 pin or its alternate-function pin and pulses are output at an unintended timing because the external trigger is valid.
chapter 8 timer/counter function user?s manual u14665ej2v0um 227 (7) operation of ovfn flag (a) ovfn flag set the ovfn flag is set to 1 in the following case: selection of mode in which tm0 is cleared and started on match between tmn and crn0, or mode in which tm0 is cleared and started at the tin0 valid edge, or free-running mode crn0 set to ffffh when tmn counts up from ffffh to 0000h figure 8-28. operation timing of ovfn flag (b) clear ovfn flag even if the ovfn flag is cleared before the next count clock is counted (before tmn becomes 0001h) after tmn has overflowed, the ovfn flag is set again and the clear becomes invalid. (8) conflicting operations (a) if the read period and capture trigger input conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, if the read period and capture trigger input conflict, the capture trigger has priority. the read data of crn0 and crn1 is undefined. (b) if the match timings of the write period and tmn conflict when 16-bit capture/compare registers n0 and n1 (crn0, crn1) are used as capture registers, because match detection cannot be performed correctly if the match timings of the write period and 16-bit timer register n (tmn) conflict, do not write to crn0 and crn1 close to the match timing. count pulse crn0 0001h 0000h ffffh fffeh ffffh tmn ovfn inttmn0
chapter 8 timer/counter function 228 user?s manual u14665ej2v0um (9) timer operation (a) crn1 capture even if 16-bit timer register n (tmn) is read, a capture to 16-bit capture/compare register n1 (crn1) is not performed. (b) acknowledgement of tin0 and tin1 pins when the timer is stopped, input signals to the tin0 and tin1 pins are not acknowledged, regardless of the cpu operation. (c) one-shot pulse output the one-shot pulse output operates correctly only in free-running mode or in clear & start mode set at the valid edge of the tin0 pin. a one-shot pulse cannot be output in the clear & start mode set on a match of tmn and crn0 because an overflow does not occur. (10) capture operation (a) if the valid edge of tin0 is specified for the count clock when the valid edge of tin0 is specified for the count clock, the capture register with tin0 specified as a trigger will not operate correctly. (b) if both rising and falling edges are selected as the valid edge of tin0 if both rising and falling edges are selected as the valid edge of tin0, a capture operation is not performed. (c) to capture the signals correctly from tin0 and tin1 the capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 (prmn0, prmn1) in order to correctly capture the signals from tin1 and tin0. (d) interrupt request input although a capture operation is performed at the falling edge of the count clock, interrupt request inputs (inttmn0, inttmn1) are generated at the falling edge of the next count clock. (11) compare operation (a) when rewriting crn0 and crn1 during timer operation when rewriting 16-bit timer capture/compare registers n0 and n1 (crn0, crn1), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) when crn0 and crn1 are set to compare mode when crn0 and crn1 are set to compare mode, they do not perform a capture operation even if a capture trigger is input.
chapter 8 timer/counter function user?s manual u14665ej2v0um 229 (12) edge detection (a) when the tin0 or tin1 pin is high level immediately after a system reset when the tin0 or tin1 pin is high level immediately after a system reset, if the valid edge of the tin0 or tin1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (tmn) is then enabled, the rising edge will be detected immediately. care is therefore needed when the tin0 or tin1 pin is pulled up. however, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the tin0 valid edge is used as a count clock or a capture trigger. the former is sampled by fxx/2, and the latter is sampled by the count clock selected using prescaler mode registers n0 or n1 (prmn0, prmn1). detecting the valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice.
chapter 8 timer/counter function 230 user?s manual u14665ej2v0um 8.3 16-bit timer (tm2 to tm6) remark n = 2 to 6 in section 8.3. 8.3.1 functions tm2 to tm5 have the following functions. ? pwm output with 16-bit resolution ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution tm6 has the following function. ? interval timer with 16-bit resolution figure 8-29. block diagram of tm2 to tm6 notes 1. the count clock is set by the tcln register. 2. serial interface clock (tm2 and tm3 only) remarks 1. ? ] ? is a signal that can be directly connected to a port. 2. m = 2 to 5 16-bit compare register n (crn) 16-bit counter n (tmn) match ovf mask circuit tcen0 selector clear 4 tcln2 tcln1 tcln0 timer clock selection register n0, n1 (tcln0, tcln1) internal bus tmcn06 0 lvsm0 lvrm0 tmcm01 toem0 timer mode control register n (tmcn0) s q r invert level s r inv q selector inttmn selector tom internal bus selector count clock n o t e 1 tim tcln3 n o t e 2
chapter 8 timer/counter function user?s manual u14665ej2v0um 231 8.3.2 configuration timer n includes from the following hardware. table 8-5. configuration of timers 2 to 6 item configuration timer registers 16-bit counters 2 to 6 (tm2 to tm6) registers 16-bit compare registers 2 to 6 (cr2 to cr6) timer outputs to2 to to5 control registers timer clock selection registers 20 to 60 and 21 to 61 (tcl20 to tcl60 and tcl21 to tcl61) 8-bit timer mode control registers 20 to 60 (tmc20 to tmc60) (1) 16-bit counters 2 to 6 (tm2 to tm6) tmn is a 16-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 0000h. (1) reset is input. (2) tcen is cleared. (3) tmn and crn match in the clear and start mode that occurs when tmn and crn0 match. (2) 16-bit compare registers 2 to 6 (cr2 to cr6) the value set in crn is always compared to the count in 16-bit counter n (tmn). if the two values match, an interrupt request (inttmn) is generated (except in the pwm mode).
chapter 8 timer/counter function 232 user?s manual u14665ej2v0um 8.3.3 timer n control register the following two types of registers control timer n. ? timer clock selection registers n0, n1 (tcln0, tcln1) ? 16-bit timer mode control register n (tmcn) (1) timer clock selection registers 20 to 60 and 21 to 61 (tcl20 to tcl60 and tcl21 to tcl61) these registers set the count clock of timer n. tcln0 and tcln1 are set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff244h, fffff0e4h 76543210 tclm0 0 0 0 0 0 tclm2 tclm1 tclm0 (m = 2, 3) after reset: 00h r/w address: fffff24eh, fffff2eeh 76543210 tclm10000000tclm3 (m = 2, 3) count cock selection f xx tclm3 tclm2 tclm1 tclm0 count clock 16 mhz 8 mhz 0000tim fa lling edge ?? 0001tim rising edge ?? 0010f xx /4 250 ns 500 ns 0011f xx /8 500 ns 1 s 0100f xx /16 1 s2 s 0101f xx /32 2 s4 s 0110f xx /128 8 s 16 s 0111f xx /512 32 s 64 s 1000setting prohibited ?? 1001setting prohibited ?? 1010f xx /64 4 s8 s 1011f xx /256 16 s 32 s 1100setting prohibited ?? 1101setting prohibited ?? 1110setting prohibited ?? 1111setting prohibited ?? cautions 1. when tclm0 and tclm1 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 to in tclm0 to 0, and bits 1 to 7 in tclm1 to 0.
chapter 8 timer/counter function user?s manual u14665ej2v0um 233 after reset: 00h r/w address: fffff264h, fffff334h 76543210 tclm0 0 0 0 0 0 tclm2 tclm1 tclm0 (m = 4, 5) after reset: 00h r/w address: fffff26eh, fffff33eh 76543210 tclm10000000tclm3 (m = 4, 5) count clock selection f xx tclm3 tclm2 tclm1 tclm0 count clock 16 mhz 8 mhz 0000tim fa lling edge ?? 0001tim rising edge ?? 0010f xx /4 250 ns 500 ns 0011f xx /8 500 ns 1 s 0100f xx /16 1 s2 s 0101f xx /32 2 s4 s 0110f xx /128 8 s 16 s 0 1 11 f xt (subsystem clock) 30.5 s 30.5 s 1000setting prohibited ?? 1001setting prohibited ?? 1010f xx /64 4 s8 s 1011f xx /256 16 s 32 s 1100setting prohibited ?? 1101setting prohibited ?? 1110setting prohibited ?? 1111setting prohibited ?? cautions 1. when tclm0 and tclm1 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 of tclm0 and bits 1 to 7 of tclm1 to 0.
chapter 8 timer/counter function 234 user?s manual u14665ej2v0um after reset: 00h r/w address: fffff284h 76543210 tcl60 0 0 0 0 0 tcl62 tcl61 tcl60 after reset: 00h r/w address: fffff28eh 76543210 tcl610000000tcl63 count clock selection f xx tcl63 tcl62 tcl61 tcl60 count clock 16 mhz 8 mhz 0000 setting prohibited ?? 0001 setting prohibited ?? 0010 f xx /4 250 ns 500 ns 0011 f xx /8 500 ns 1 s 0100 f xx /16 1 s2 s 0101 f xx /32 2 s4 s 0110 f xx /64 4 s8 s 0111 f xx /128 8 s 16 s 1000 setting prohibited ?? 1001 setting prohibited ?? 1010 f xx /256 16 s 32 s 1011 f xx /512 32 s 64 s 1100 setting prohibited ?? 1101 setting prohibited ?? 1110 setting prohibited ?? 1111 tm0 overflow signal ?? cautions 1. when tcl60 and tcl61 are overwritten by different data, write after temporarily stopping the timer. 2. always set bits 3 to 7 of tcl60 and bits 1 to 7 of tcl61 to 0.
chapter 8 timer/counter function user?s manual u14665ej2v0um 235 (2) 16-bit timer mode control registers 20 to 60 (tmc20 to tmc60) the tmcn0 register makes the following five settings. (1) controls the counting by 16-bit counter n (tmn) (2) selects the operation mode of 16-bit counter n (tmn) (3) sets the state of the timer output flip-flop (4) controls the timer flip-flop or selects the active level in the pwm (free-running) mode (5) controls timer output tmcn0 is set by an 8- or 1-bit memory manipulation instruction. reset input sets these registers to 04h (although the state of hardware is initialized to 04h, 00h is read when reading).
chapter 8 timer/counter function 236 user?s manual u14665ej2v0um after reset: 04h r/w address: tmc20 fffff246h tmc50 fffff336h tmc30 fffff0e6h tmc60 fffff286h tmc40 fffff266h 76543210 tmcn0 tcen0 tmcn06 0 0 lvsm0 lvrm0 tmcm01 toem0 (m = 2 to 5) tcen0 tmn count operation control 0 counting is disabled after the counter is cleared to 0 (prescaler disabled) 1 start count operation tmcn06 tmn operating mode selection 0 clear & start mode when tmn and crn match 1 pwm (free-running) mode lvsm0 lvrm0 setting state of timer output flip-flop 0 0 not change 0 1 reset timer output flip-flop to 0 1 0 set timer output flip-flop to 1 1 1 setting prohibited other than pwm (free-running) mode (tmcn06 = 0) pwm (free-running) mode (tmcn06 = 1) tmcm01 controls timer f/f selects active level 0 inversion operation disabled active high 1 inversion operation enabled active low toem0 timer output control 0 output disabled (port mode) 1 output enabled cautions 1. when using as the timer output pin (tom), set the port value to 0 (port mode output). a logical sum (ored) value of the timer output value is output. 2. since tom and tim are the same alternate-function pin, only one function can be used. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tcem0 = 0. 2. if lvsm0 and lvrm0 are read after setting data, 0 is read.
chapter 8 timer/counter function user?s manual u14665ej2v0um 237 8.4 16-bit timer (tm2 to tm6) operation remark n = 2 to 6 and m = 2 to 5 in section 8.4. 8.4.1 operation as interval timer the timer operates as an interval timer that repeatedly generates interrupts at the interval specified by the count value preset to 16-bit compare register n (crn). if the count value of 16-bit counter n (tmn) matches the set value of crn, the value of tmn is cleared to 0 and the timer continues counting, and an interrupt request signal (inttmn) is generated. the tmn count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of timer clock selection register n0 (tcln0) and by bit 0 (tcln3) of timer clock selection register n1 (tcln1). setting method (1) set each register. ? tcln0, tcln1: selects the count clock. ? crn: compare value ? tmcn0: selects the clear and start mode when tmn and crn match. (tmcn0 = 0000 xxx0b, = don?t care) (2) when tcen0 = 1 is set, counting starts. (3) when the values of tmn and crn match, inttmn is generated (tmn is cleared to 0000h). (4) inttmn is then repeatedly generated during the same interval. when counting stops, set tcen0 = 0. figure 8-30. timing of interval timer operation (1/2) basic operation tmn count value crn 0000h 0001h n 0000h 0001h 0000h 0001h n n count start clear clear nn n n interrupt acknowledgement interrupt acknowledgement tcen0 inttmn ton interval time interval time interval time count clock t remark interval time = (n + 1) t; n = 0000h to ffffh
chapter 8 timer/counter function 238 user?s manual u14665ej2v0um figure 8-30. timing of interval timer operation (2/2) when crn = 0000h when crn = ffffh 0001h fffeh ffffh 0000h fffeh ffffh 0000h ffffh ffffh ffffh count clock tmn crn tcen0 inttmn ton interrupt acknowledgement interval time t interrupt acknowledgement count clock crn tcen0 inttmn ton tmn 0000h 0000h 0000h 0000h 0000h interval time t
chapter 8 timer/counter function user?s manual u14665ej2v0um 239 8.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to tim. each time a valid edge specified by timer clock selection register m0, m1 (tclm0, tclm1) is input, tmm is incremented. the edge setting can be selected to be either a rising or falling edge. if the total of tmm and the value of 16-bit compare register m (crm) match, tmm is cleared to 0 and an interrupt request signal (inttmm) is generated. inttmm is generated each time the tmm value matches the crm value. figure 8-31. timing of external event counter operation (with rising edge specified) tim tmm count value 0005h 0004h 0003h 0002h 0001h 0000h n-1 n crm inttmm n 0000h 0001h 0002h 0003h
chapter 8 timer/counter function 240 user?s manual u14665ej2v0um 8.4.3 operation as square-wave output a square-wave with any frequency is output at the interval preset to 16-bit compare register m (crm). by setting bit 0 (toem0) of 16-bit timer mode control register m0 (tmcm0) to 1, the output state of tom is inverted at an interval specified by the count value preset to crm. therefore, a square-wave of any frequency (duty factor = 50%) can be output. setting method (1) set the registers. ? sets the port latch and port mode register to 0 ? tclm0, tclm1: selects the count clock ? crm: compare value ? tmcm0: clear and start mode when tmm and crm match lvsm0 lvrm0 setting state of timer output flip-flop 1 0 high-level output 0 1 low-level output inversion of timer output flip-flop enabled timer output enabled toem0 = 1 (2) when tcem0 = 1 is set, the counter starts operating. (3) if the values of tmm and crm match, the timer output flip-flop inverts. also, inttmm is generated and tmm is cleared to 0000h. (4) the timer output flip-flop is then inverted at the same interval and a square-wave is output from tom. figure 8-32. square-wave output operation timing note the initial value of tom output can be set using bits 3 and 2 (lvsm0, lvrm0) of the tmcm0 register. 0000h 0000h 0001h 0002h n-1 n 0001h 0002h n n-1 n 0000h count clock crm tom tmm count value count start
chapter 8 timer/counter function user?s manual u14665ej2v0um 241 8.4.4 operation as 16-bit pwm output by setting bit 6 (tmcm6) of 16-bit timer mode control register m0 (tmcm0) to 1, the timer operates as a pwm output. pulses with the duty factor determined by the value set in 16-bit compare register m (crm) are output from tom. set the width of the active level of the pwm pulse to crm. the active level can be selected by bit 1 (tmcm01) of tmcm0. the count clock can be selected by bits 0 to 2 (tclm0 to tclm2) of timer clock selection register m0 (tclm0) and by bit 0 (tclm3) of timer clock selection register m1 (tclm1). the pwm output can be enabled and disabled by bit 0 (toem0) of tmcm0. caution crm can be rewritten only once in one period while in pwm mode. (1) basic operation of the pwm output setting method (1) set the port latch and port mode register n to 0. (2) set the active level width in 16-bit compare register m (crm). (3) select the count clock using timer clock selection register m0, m1 (tclm0, tclm1). (4) set the active level in bit 1 (tmcm01) of tmcm0. (5) if bit 7 (tcem0) of tmcm0 is set to 1, counting starts. to stop counting, set tcem0 to 0. pwm output operation (1) when counting starts, the pwm output (output from tom) outputs an inactive level until an overflow occurs. (2) when an overflow occurs, the active level specified in step (1) in the setting method is output. the active level is output until crm and the count of 8-bit counter m (tmm) match. (3) the pwm output after crm and the count match is the inactive level until an overflow occurs again. (4) steps (2) and (3) repeat until counting stops. (5) if counting is stopped by tcem0 = 0, pwm output goes to the inactive level.
chapter 8 timer/counter function 242 user?s manual u14665ej2v0um (a) basic operation of pwm output figure 8-33. timing of pwm output basic operation (active level = h) count clock 0000h tmm crm tcem0 inttmm tom active level inactive level active level 0001h ffffh 0000h 0001h 0002h n n+1 ffffh 0000h 0001h 0002h m 0000h n when crm = 0 count clock tmm crm tcem0 inttmm tom inactive level inactive level 0000h 0001h ffffh 0000h 0001h 0002h nn+1n+2 ffffh 0000h 0001h 0002h m 0000h 0000h when crm = ffffh count clock tmm crm tcem0 inttmm tom inactive level inactive level active level a ctive level inactive level 0000h 0001h ffffh 0000h 0001h 0002h n n+1 n+2 ffffh 0000h 0001h 0002h m 0000h ffffh
chapter 8 timer/counter function user?s manual u14665ej2v0um 243 8.4.5 cautions (1) error when the timer starts an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit counter n (tmn) is started asynchronously to the count pulse. figure 8-34. start timing of timer n (2) tmn readout during timer operation since reading out tmn during operation occurs while the selected clock is temporarily stopped, select a high- or low-level waveform that is longer than the selected clock. 0000h 0001h 0002h 0003h 0004h timer starts tmn count value count pulse
user?s manual u14665ej2v0um 244 chapter 9 watch timer function 9.1 function the watch timer has the following functions. ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 9-1. block diagram of watch timer f w /2 10 selector 11-bit prescaler f w /2 8 f w /2 7 f w /2 6 f w /2 5 f w /2 4 5-bit counter intwtn intwtni wtnm0 wtnm1 wtnm3 wtnm4 wtnm5 wtnm6 wtnm7 watch timer mode control register (wtnm) f xx internal bus clear clear wtnm2 f xt f w /2 9 f w /2 11 wtncs1 wtncs0 selector selector selector watch timer clock selection register (wtncs) 3 f w remark f xx : main system clock frequency f xt : subsystem clock frequency f w : watch timer clock frequency
chapter 9 watch timer function user?s manual u14665ej2v0um 245 (1) watch timer the watch timer generates an interrupt request (intwtn) at time intervals of 0.5 second or 0.25 second using the main system clock or subsystem clock. (2) interval timer the watch timer generates an interrupt request (intwtni) at time intervals specified in advance. table 9-1. interval time of interval timer interval time f xt = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.4 ms remark watch timer clock frequency 9.2 configuration the watch timer includes the following hardware. table 9-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control registers watch timer mode control register (wtnm) watch timer clock selection register (wtncs)
chapter 9 watch timer function user?s manual u14665ej2v0um 246 9.3 watch timer control register the watch timer mode control register (wtnm) and watch timer clock selection register (wtncs) control the watch timer. the watch timer should be operated after setting the count clock. (1) watch timer mode control register (wtnm) this register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. wtnm is set by an 8- or 1-bit memory manipulation instruction. reset input clears wtnm to 00h. after reset: 00h r/w address: fffff360h 76543210 wtnm wtnm7 wtnm6 wtnm5 wtnm4 wtnm3 wtnm2 wtnm1 wtnm0 wtnm6 wtnm5 wtnm4 selection of interval time of prescaler 0002 4 /f w (488 s) 0012 5 /f w (977 s) 0102 6 /f w (1.95 ms) 0112 7 /f w (3.91 ms) 1002 8 /f w (7.81 ms) 1012 9 /f w (15.6 ms) 1102 10 /f w (31.2 ms) 1112 11 /f w (62.4 ms) wtnm3 wtnm2 selection of set time of watch flag 002 14 /f w (0.5 s) 012 13 /f w (0.25 s) 102 5 /f w (977 s) 112 4 /f w (488 s) wtnm1 operation of 5-bit counter 0 cleared after operation stops 1 operation starts wtnm0 operation of watch timer 0 operation stopped (both prescaler and 5-bit counter cleared) 1 operation enabled remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz. 3. for the settings of wtnm7, refer to 9.3 (2) watch timer clock selection register (wtncs) .
chapter 9 watch timer function user?s manual u14665ej2v0um 247 (2) watch timer clock selection register (wtncs) this register selects the count clock of the watch timer. wtncs is set by an 8-bit memory manipulation instruction. reset input clears wtncs to 00h. caution do not change the contents of the wtnm and wtncs registers (interval time, watch flag set time, count clock) during a watch timer operation. after reset: 00h r/w address: fffff364h 76543210 wtncs000000wtncs1wtncs0 wtncs1 wtncs0 wtnm7 selection of count clock main clock frequency 000f xx /2 7 4.194 mhz 001f xt (subsystem clock) ? 010f xx /3 2 6 6.291 mhz 011f xx /2 8 8.388 mhz 1 0 0 setting prohibited ? 1 0 1 setting prohibited ? 110f xx /3 2 7 12.582 mhz 1 1 1 setting prohibited ? remark wtnm7 is bit 7 of the wtnm register
chapter 9 watch timer function user?s manual u14665ej2v0um 248 9.4 operation 9.4.1 operation as watch timer the watch timer operates with time intervals of 0.5 second with the subsystem clock (32.768 khz). the watch timer generates an interrupt request at fixed time intervals. the count operation of the watch timer is started when bits 0 (wtnm0) and 1 (wtnm1) of the watch timer mode control register (wtnm) are set to 1. when these bits are cleared to 0, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. setting the wtnm1 bit to 0 can clear the watch timer. an error of up to 15.6 ms may occur at this time. setting the wtnm0 bit to 0 can clear the interval timer. however, an error up to 0.5 sec. may occur after a watch timer overflow (intwtn) because the 5-bit counter is also cleared.
chapter 9 watch timer function user?s manual u14665ej2v0um 249 9.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. the interval time can be selected by bits 4 to 6 (wtnm4 to wtnm6) of the watch timer mode control register (wtnm). table 9-2. interval time of interval timer wtnm6 wtnm5 wtnm4 interval time f w = 32.768 khz 000 2 4 1/f w 488 s 001 2 5 1/f w 977 s 010 2 6 1/f w 1.95 ms 011 2 7 1/f w 3.91 ms 100 2 8 1/f w 7.81 ms 101 2 9 1/f w 15.6 ms 110 2 10 1/f w 31.2 ms 111 2 11 1/f w 62.4 ms remark f w : watch timer clock frequency figure 9-2. operation timing of watch timer/interval timer start 5-bit counter overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) count clock f w or f w /2 9 watch timer interrupt intwtn interval timer interrupt intwtni nt nt remark f w : watch timer clock frequency the values in parentheses apply when the count clock is operating at f w = 32.768 khz. n: number of interval timer operations
chapter 9 watch timer function user?s manual u14665ej2v0um 250 9.4.3 cautions it takes some time to generate the first watch timer interrupt request (intwtn) after operation is enabled (wtnm1 and wtnm0 bits of wtnm register = 1). figure 9-3. watch timer interrupt request (intwtn) generation (interrupt period = 0.5 s) it takes 0.515625 s to generate the first intwtn (2 9 1/32.768 = 0.015625 s longer). intwtn is then generated every 0.5 s. 0.5 s 0.5 s 0.515625 s wtnm0, wtnm1 intwtn
user?s manual u14665ej2v0um 251 chapter 10 watchdog timer function 10.1 functions the watchdog timer has the following functions. ? watchdog timer ? interval timer ? oscillation stabilization time selection caution use the watchdog timer mode register (wdtm) to select the watchdog timer mode or the interval timer mode. figure 10-1. block diagram of watchdog timer internal bus osts0 osts1 osts2 osts wdtm4 run wdtm wdcs wdcs0 wdcs1 wdcs2 3 intwdt note 1 intwdtm note 2 3 output controller prescaler selector f xx /2 24 f xx /2 12 f xx /2 22 f xx /2 21 f xx /2 20 f xx /2 19 f xx /2 18 f xx /2 17 f xx /2 16 run clear osc selector notes 1. in watchdog timer mode 2. in interval timer mode remark f xx : main clock frequency
chapter 10 watchdog timer function 252 user?s manual u14665ej2v0um (1) watchdog timer mode this mode detects an inadvertent program loop. when a loop is detected, a non-maskable interrupt can be generated. table 10-1. loop detection time of watchdog timer loop detection time clock f xx = 16 mhz f xx = 8 mhz 2 16 /f xx 4.1 ms 8.2 ms 2 17 /f xx 8.2 ms 16.4 ms 2 18 /f xx 16.4 ms 32.8 ms 2 19 /f xx 32.8 ms 65.5 ms 2 20 /f xx 65.5 ms 131.1 ms 2 21 /f xx 131.1 ms 262.1 ms 2 22 /f xx 262.1 ms 524.3 ms 2 24 /f xx 1.05 s 2.10 s (2) interval timer mode interrupts are generated at a preset time interval. table 10-2. interval time of interval timer interval time clock f xx = 16 mhz f xx = 8 mhz 2 16 /f xx 4.1 ms 8.2 ms 2 17 /f xx 8.2 ms 16.4 ms 2 18 /f xx 16.4 ms 32.8 ms 2 19 /f xx 32.8 ms 65.5 ms 2 20 /f xx 65.5 ms 131.1 ms 2 21 /f xx 131.1 ms 262.1 ms 2 22 /f xx 262.1 ms 524.3 ms 2 24 /f xx 1.05 s 2.10 s
chapter 10 watchdog timer function user?s manual u14665ej2v0um 253 10.2 configuration the watchdog timer includes the following hardware. table 10-3. watchdog timer configuration item configuration control registers oscillation stabilization time selection register (osts) watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) 10.3 watchdog timer control register the watchdog timer is controlled by the following registers. ? oscillation stabilization time selection register (osts) ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register (wdtm) (1) oscillation stabilization time selection register (osts) this register selects the oscillation stabilization time after a reset is applied or the stop mode is canceled until the oscillation is stable. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. after reset: 04h r/w address: fffff380h 765 4 3 21 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 16 mhz 8 mhz 0002 16 /f xx 4.1 ms 8.2 ms 0012 18 /f xx 16.4 ms 32.8 ms 0102 19 /f xx 32.8 ms 65.5 ms 0112 20 /f xx 65.5 ms 131.1 ms 1002 21 /f xx (after reset) 131.1 ms 262.1 ms other than above setting prohibited
chapter 10 watchdog timer function 254 user?s manual u14665ej2v0um (2) watchdog timer clock selection register (wdcs) this register selects the overflow times of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. after reset: 00h r/w address: fffff382h 7654321 0 wdcs 0 0 0 0 0 wdcs2 wdcs1 wdcs0 watchdog timer/interval timer overflow time f xx wdcs2 wdcs1 wdcs0 clock 16 mhz 8 mhz 0002 16 /f xx 4.1 ms 8.2 ms 0012 17 /f xx 8.2 ms 16.4 ms 0102 18 /f xx 16.4 ms 32.8 ms 0112 19 /f xx 32.8 ms 65.5 ms 1002 20 /f xx 65.5 ms 131.1 ms 1012 21 /f xx 131.1 ms 262.1 ms 1102 22 /f xx 262.1 ms 524.3 ms 1112 24 /f xx 1.05 s 2.10 s
chapter 10 watchdog timer function user?s manual u14665ej2v0um 255 (3) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables and disables counting. wdtm is set by an 8- or 1-bit memory manipulation instruction. reset input sets wdtm to 00h. after reset: 00h r/w address: fffff384h 76543210 wdtm run 0 0 wdtm4 0 0 0 0 run operation mode selection for the watchdog timer note 1 0 count disabled 1 count cleared and counting starts wdtm4 operation mode selection for the watchdog timer note 2 0 interval timer mode (if an overflow occurs, a maskable interrupt, intwdtm, is generated.) 1 watchdog timer mode 1 (if an overflow occurs, a non-maskable interrupt, intwdt, is generated.) notes 1. once run is set (1), the register cannot be cleared (0) by software. therefore, when the count starts, the count cannot be stopped except by reset input. 2. once wdtm4 is set (1), the register cannot be cleared (0) by software. caution if run is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 2 12 /f xx seconds shorter than the set time.
chapter 10 watchdog timer function 256 user?s manual u14665ej2v0um 10.4 operation 10.4.1 operation as watchdog timer set bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 1 to operate as a watchdog timer to detect an inadvertent program loop. setting bit 7 (run) of wdtm to 1 starts the count. after counting starts, if run is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again. if run is not set to 1 and the loop detection time has elapsed, a non-maskable interrupt (intwdt) is generated (no reset functions). the watchdog timer stops running in the stop mode and idle mode. consequently, set run to 1 and clear the watchdog timer before entering the stop mode or idle mode. do not set the watchdog timer when using the halt mode since the watchdog timer continues running in halt mode. cautions 1. the actual loop detection time may be up to 2 12 /f xx seconds shorter than the set time. 2. when the subsystem clock is selected for the cpu clock, the watchdog timer stops counting (pauses). table 10-4. loop detection time of watchdog timer loop detection time clock f xx = 16 mhz f xx = 8 mhz 2 16 /f xx 4.1 ms 8.2 ms 2 17 /f xx 8.2 ms 16.4 ms 2 18 /f xx 16.4 ms 32.8 ms 2 19 /f xx 32.8 ms 65.5 ms 2 20 /f xx 65.5 ms 131.1 ms 2 21 /f xx 131.1 ms 262.1 ms 2 22 f xx 262.1 ms 524.3 ms 2 24 /f xx 1.05 s 2.10 s
chapter 10 watchdog timer function user?s manual u14665ej2v0um 257 10.4.2 operation as interval timer set bit 4 (wdtm4) to 0 in the watchdog timer mode register (wdtm) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. when operating as an interval timer, the interrupt mask flag (wdtmk) of the wdtic register and the priority setting flag (wdtpr0 to wdtpr2) become valid, and a maskable interrupt (intwdtm) can be generated. the default priority of intwdtm has the highest priority setting of the maskable interrupts. the interval timer continues operating in the halt mode and stops in the stop mode and idle mode. therefore, before entering the stop mode/idle mode, set the run bit of wdtm register to 1 to clear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as reset is not input. 2. the interval time immediately after being set by wdtm may be up to 2 12 /f xx seconds shorter than the set time. 3. when the subsystem clock is selected for the cpu clock, the watchdog timer stops counting (pauses). table 10-5. interval time of interval timer interval time clock f xx = 16 mhz f xx = 8 mhz 2 16 /f xx 4.1 ms 8.2 ms 2 17 /f xx 8.2 ms 16.4 ms 2 18 /f xx 16.4 ms 32.8 ms 2 19 /f xx 32.8 ms 65.5 ms 2 20 /f xx 65.5 ms 131.1 ms 2 21 /f xx 131.1 ms 262.1 ms 2 22 /f xx 262.1 ms 524.3 ms 2 24 /f xx 1.05 s 2.10 s
chapter 10 watchdog timer function 258 user?s manual u14665ej2v0um 10.5 standby function control register the wait time from when the stop mode is canceled until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. after reset: 04h r/w address: fffff380h 76543210 osts00000osts2osts1osts0 oscillation stabilization time selection f xx osts2 osts1 osts0 clock 16 mhz 8 mhz 0002 16 /f xx 4.1 ms 8.2 ms 0012 18 /f xx 16.4 ms 32.8 ms 0102 19 /f xx 32.8 ms 65.5 ms 0112 20 /f xx 65.5 ms 131.1 ms 1002 21 /f xx (after reset) 131.1 ms 262.1 ms other than above setting prohibited caution the wait time at the cancelation of the stop mode does not include the time (?a? in the figure below) until clock oscillation starts after stop mode is canceled by reset input or interrupt generation. vss stop mode cancelation a voltage waveform at x1 pin
user?s manual u14665ej2v0um 259 chapter 11 serial interface function 11.1 overview the v850/sf1 incorporates the following serial interfaces. ? channel 0: 3-wire serial i/o (csi0)/i 2 c0 note ? channel 1: 3-wire serial i/o (csi1)/asynchronous serial interface (uart0) ? channel 3: 3-wire serial i/o (csi3)/asynchronous serial interface (uart1) ? channel 4: 8 to 16-bit variable-length 3-wire serial i/o (csi4) note i 2 c0 supports multiple masters. either 3-wire serial i/o or i 2 c can be used as a serial interface. 11.2 3-wire serial i/o (csi0, csi1, csi3) remark n = 0, 1, 3 in section 11.2. csin has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sckn), a serial output line (son), and a serial input line (sin). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clocked serial interface, a display controller, etc.
chapter 11 serial interface function user?s manual u14665ej2v0um 260 11.2.1 configuration csin includes the following hardware. table 11-1. configuration of csin item configuration registers serial i/o shift register n (sion) control registers serial operation mode register n (csimn) serial clock selection register n (csisn) figure 11-1. block diagram of 3-wire serial i/o tmx output clock selection sckn son sin intcsin internal bus selector 8 serial clock controller serial clock counter serial i/o shift register n (sion) interrupt generator remark the following indicates the tmx output. when n = 0 or 3: tm2 when n = 1: tm3 (1) serial i/o shift register n (sion) sion is an 8-bit register that performs parallel-serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. sion is set by an 8-bit memory manipulation instruction. when ?1? is set to bit 7 (csien) of serial operation mode register n (csimn), a serial operation can be started by writing data to or reading data from sion. when transmitting, data written to sion is output via the serial output (son). when receiving, data is read from the serial input (sin) and written to sion. reset input resets these registers to 00h. caution do not access sion except via the transfer start trigger during a transfer operation (read is disabled when moden = 0 and write is disabled when moden = 1).
chapter 11 serial interface function user?s manual u14665ej2v0um 261 11.2.2 csin control registers csin is controlled by the following registers. ? serial operation mode register n (csimn) ? serial clock selection register n (csisn)
chapter 11 serial interface function user?s manual u14665ej2v0um 262 (1) serial operation mode register n (csimn) csimn is used to enable or disable the serial clock, operation modes, and specific operations of serial interface channel n. csimn can be set by an 8- or 1-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim3 fffff2d2h 76543210 csimn csien 0 0 0 0 moden scln1 scln0 sion operation enable/disable specification shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 transfer operation mode flag operation mode transfer start trigger son output 0 transmit/receive mode sion write normal output 1 receive-only mode sion read port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 at n = 0, 3: tm2 output at n = 1: tm3 output 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 notes 1. the sin, son, and sckn pins are used as port function pins when csien = 0 (sion operation stop status). 2. when csien = 1 (sion operation enable status), the port function is available for the sin pin when only using the transmit function and son pin when only using the receive function. caution do not perform bit manipulation of scln1 and scln0. remarks 1. refer to 11.2.2 (2) serial clock selection register n (csisn) for the scln2 bit. 2. when the selection clock is output as a timer, pins p30/to2/ti2 and p31/to3/ti3 do not need to be set in timer output mode. csien moden
chapter 11 serial interface function user?s manual u14665ej2v0um 263 (2) serial clock selection register n (csisn) csisn is used to set the serial clock of serial interface channel n. csisn can be set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset : 00h r/w address: csis0 fffff2a4h csis1 fffff2b4h csis3 fffff2d4h 76543210 csisn0000000scln2 remark refer to 11.2.2 (1) serial operation mode register n (csimn) for the setting of the scln2 bit. 11.2.3 operations the csin has the following two operation modes. ? operation stopped mode ? 3-wire serial i/o mode (1) operation stopped mode in this mode, serial transfers are not performed and therefore power consumption can be reduced. when in operation stopped mode, sin, son, and sckn pins can be used as normal i/o port pins. (a) register settings operation stopped mode is set via the csien bit of serial operation mode register n (csimn). figure 11-2. csimn setting (operation stopped mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim3 fffff2d2h 76543210 csimn csien 0 0 0 0 moden scln1 scln0 sion operation enable/disable specification shift register operation serial counter port 0 operation disabled cleared port function csien
chapter 11 serial interface function user?s manual u14665ej2v0um 264 (2) 3-wire serial i/o mode 3-wire serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sckn), a serial output line (son), and a serial input line (sin). (a) register settings 3-wire serial i/o mode is set by serial operation mode register n (csimn). figure 11-3. csimn setting (3-wire serial i/o mode) after reset : 00h r/w address: csim0 fffff2a2h csim1 fffff2b2h csim3 fffff2d2h 76543210 csimn csien 0 0 0 0 moden scln1 scln0 sion operation enable/disable specification shift register operation serial counter port 1 operation enabled count operation enabled serial function + port function transfer operation mode flag operation mode transfer start trigger son output 0 transmit/receive mode write to sion normal output 1 receive-only mode read from sion port function scln2 scln1 scln0 clock selection 0 0 0 external clock input (sckn) 0 0 1 when n = 0, 3: tm2 output when n = 1: tm3 output 010f xx /8 011f xx /16 1 0 0 setting prohibited 1 0 1 setting prohibited 110f xx /32 111f xx /64 remark when the selection clock is output as a timer, pins p30/to2/ti2 and p31/to3/ti3 do not need to be set in timer output mode. csien moden
chapter 11 serial interface function user?s manual u14665ej2v0um 265 (b) communication operations in 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received in synchronization with the serial clock. serial i/o shift register n (sion) is shifted in synchronization with the falling edge of the serial clock. transmission data is held in the son latch and is output from the son pin. data that is received via the sin pin in synchronization with the rising edge of the serial clock is latched to sion. completion of an 8-bit transfer automatically stops operation of sion and sets the interrupt request flag (intcsin). figure 11-4. timing of 3-wire serial i/o mode (c) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial i/o shift register n (sion). ? the sion operation control bit (csien) = 1 ? after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. the transfer data to sion is set as follows. ? transmit/receive mode when csien = 1 and moden = 0, transfer starts when writing to sion. ? receive-only mode when csien = 1 and moden = 1, transfer starts when reading from sion. caution after data has been written to sion, transfer will not start even if the csien bit value is set to 1. completion of an 8-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsin). sin di7 di6 di5 di4 di3 di2 di1 di0 intcsin serial clock 1 son do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the falling edge of the serial clock
chapter 11 serial interface function user?s manual u14665ej2v0um 266 11.3 i 2 c bus to use the i 2 c bus function, set the p10/sda0 and p12/scl0 pins to n-ch open drain output. i 2 c0 has the following two modes. ? operation stopped mode ? i 2 c (inter ic) bus mode (multiple masters supported) (1) operation stopped mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multiple masters support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock line (scl0) and a serial data bus line (sda0). this mode complies with the i 2 c bus format and the master device can output ?start condition?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since scl0 and sda0 are open-drain outputs, the i 2 c0 requires pull-up resistors for the serial clock line and the serial data bus line.
chapter 11 serial interface function user?s manual u14665ej2v0um 267 figure 11-5. block diagram of i 2 c0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator match signal iic shift register 0 (iic0) so latch iice0 d q set clear cl01, cl00 sda0 scl0 n-ch open drain output n-ch open drain output data hold time correction circuit ack detector wake up controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 f xx tm2 output lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx0 iicce01 iicce00 iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) iic clock expansion register 0 (iicce0)
chapter 11 serial interface function user?s manual u14665ej2v0um 268 a serial bus configuration example is shown below. figure 11-6. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 11 serial interface function user?s manual u14665ej2v0um 269 11.3.1 configuration i 2 c0 includes the following hardware. table 11-2. configuration of i 2 c0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic clock selection register 0 (iiccl0) iic clock expansion register 0 (iicce0) iicc function expansion register 0 (iicx0) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. iic0 can be used for both transmission and reception. write and read operations to iic0 are used to control the actual transmit and receive operations. iic0 is set by an 8-bit memory manipulation instruction. reset input sets the iic0 to 00h. (2) slave address register 0 (sva0) sva0 sets local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. reset input sets the sva0 to 00h. (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) clock selector this selects the sampling clock to be used.
chapter 11 serial interface function user?s manual u14665ej2v0um 270 (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtim0 bit note ) ? interrupt request generated when a stop condition is detected (set by spie0 bit note ) note wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock.
chapter 11 serial interface function user?s manual u14665ej2v0um 271 11.3.2 i 2 c control registers i 2 c0 is controlled by the following registers. ? iic control register 0 (iicc0) ? iic status register 0 (iics0) ? iic clock selection register 0 (iiccl0) ? iic clock expansion register 0 (iicce0) ? iic function expansion register 0 (iicx0) the following registers are also used. ? iic shift register 0 (iic0) ? slave address register 0 (sva0) (1) iic control register 0 (iicc0) iicc0 is used to enable/disable i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 can be set by an 8- or 1-bit memory manipulation instruction. reset input sets iicc0 to 00h. caution in i 2 c0 bus mode, set the port 1 mode register (pm1) as follows. in addition, set each output latch to 0. ? set p10 (sda0) to output mode (pm10 = 0) ? set p12 (scl0) to output mode (pm12 = 0)
chapter 11 serial interface function user?s manual u14665ej2v0um 272 (1/4) after reset: 00h r/w address: fffff340h 76543210 iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c0 operation enable/disable specification 0 operation stopped. iic status register 0 (iics0) preset. internal operation stopped. 1 operation enabled. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) ? cleared by instruction ? when reset is input ? set by instruction lrel0 exit from communications 0 normal operation 1 this exits from the current communication operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags are cleared. ? std0 ? ackd0 ? trc0 ? coi0 ? exc0 ? msts0 ? stt0 ? spt0 the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lrel0 = 0) note condition for setting (lrel0 = 1) ? automatically cleared after execution ? when reset is input ? set by instruction note this flag?s signal is invalid when iice0 = 0. remark std0: bit 1 of iic status register 0 (iics0) ackd0: bit 2 of iic status register 0 (iics0) trc0: bit 3 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) exc0: bit 5 of iic status register 0 (iics0) msts0: bit 7 of iic status register 0 (iics0)
chapter 11 serial interface function user?s manual u14665ej2v0um 273 (2/4) wrel0 wait cancellation control 0 wait not canceled 1 wait canceled. this setting is automatically cleared after wait is canceled. condition for clearing (wrel0 = 0) note condition for setting (wrel0 = 1) ? automatically cleared after execution ? when reset is input ? set by instruction spie0 enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spie0 = 0) note condition for setting (spie0 = 1) ? cleared by instruction ? when reset is input ? set by instruction wtim0 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clo cks, clock output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clo cks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. this bit?s setting is invalid during an address transfer and is valid as the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) note condition for setting (wtim0 = 1) ? cleared by instruction ? when reset is input ? set by instruction note this flag?s signal is invalid when iice0 = 0.
chapter 11 serial interface function user?s manual u14665ej2v0um 274 (3/4) acke0 acknowledge control 0 acknowledgement disable. 1 acknowledgement enabled. during the ninth clock period, the sda0 line is set to low level. however, ack is invalid during address transfers and is valid when exc0 = 1. condition for clearing (acke0 = 0) note condition for setting (acke0 = 1) ? cleared by instruction ? when reset is input ? set by instruction stt0 start condition trigger 0 start condition not generated. 1 when bus is released (in stop mode): generates a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level. when bus is not used: this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acke0 has been set to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the ack0 period. set during the wait period. ? cannot be set at the same time as spt0 condition for clearing (stt0 = 0) condition for setting (stt0 = 1) ? cleared by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lrel0 = 1 ? when iice0 = 0 ? cleared when reset is input ? set by instruction note this flag?s signal is invalid when iice0 = 0. remark bit 1 (stt0) is 0 if it is read immediately after data setting.
chapter 11 serial interface function user?s manual u14665ej2v0um 275 (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0 line is changed from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acke0 has been set to 0 and during the wait period after slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ack0 period. set during the wait period. ? cannot be set at the same time as stt0. ? spt0 can be set only when in master mode note . ? when wtim0 has been set to 0, if spt0 is set during the wait period that follows output of eight clo cks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtim0 should be changed from 0 to 1 during the wait period following output of eight clocks, and spt0 should be set during the wait period that follows output of the ninth clock. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) ? cleared by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lrel0 = 1 ? when iice0 = 0 ? cleared when reset is input ? set by instruction note set spt0 only in master mode. however, spt0 must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 11.3.13 cautions . caution when bit 3 (trc0) of iic status register 0 (iics0) is set to 1, wrel0 is set during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set to high impedance. remark bit 0 (spt0) is 0 if it is read immediately after data setting.
chapter 11 serial interface function user?s manual u14665ej2v0um 276 (2) iic status register 0 (iics0) iics0 indicates the status of i 2 c0. iics0 can be set by an 8- or 1-bit memory manipulation instruction. iics0 is a read-only register. reset input sets iics0 to 00h. (1/3) after reset: 00h r address: fffff342h 76543210 iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) ? when a stop condition is detected ? when ald0 = 1 ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) ? automatically cleared after iics0 is read note ? when iice0 changes from 1 to 0 ? when reset is input ? when the arbitration result is a ?loss?. exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a bit manipulation instruction is executed for bits other than iics0. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 11 serial interface function user?s manual u14665ej2v0um 277 (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input ? when the received address matches the local address (sva0) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set to high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) ? when a stop condition is detected ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? cleared by wrel0 = 1 note ? when ald0 changes from 0 to 1 ? when reset is input master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) note trc0 is cleared and the sda0 line becomes high impedance when bit 5 (wrel0) of iic control register 0 (iicc0) is set and the wait state is released at ninth clock by bit 3 (trc0) of iic status register 0 (iics0) = 1. remark wrel0: bit 5 of iic control register 0 (iicc0) lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 11 serial interface function user?s manual u14665ej2v0um 278 (3/3) ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input ? after the sda0 line is set to low level at the rising edge of the scl0?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std0 = 0) condition for setting (std0 = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel0 = 1 ? when iice0 changes from 1 to 0 ? when reset is input when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iice0 changes from 1 to 0 ? when reset is input when a stop condition is detected remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
chapter 11 serial interface function user?s manual u14665ej2v0um 279 (3) iic clock selection register 0 (iiccl0) iiccl0 is used to set the transfer clock for i 2 c0. iiccl0 can be set by an 8- or 1-bit memory manipulation instruction. bits smc0, cl01 and cl00 are set using the clx0 bit of iic function expansion register 0 (iicx0) in combination with bits iicce01 and iicce00 of iic clock expansion register 0 (iicce0) (see table 11-3 selection clock setting ). reset input sets iiccl0 to 00h. after reset: 00h r/w note address: fffff344h 76 54 3210 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 line level (valid only when iice0 = 1) 0 scl0 line was detected at low level. 1 scl0 line was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) ? when the scl0 line is at low level ? when iice0 = 0 ? when reset is input ? when the scl0 line is at high level dad0 detection of sda0 line level (valid only when iice0 = 1) 0 sda0 line was detected at low level. 1 sda0 line was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) ? when the sda0 line is at low level ? when iice0 = 0 ? when reset is input ? when the sda0 line is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. the digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc0 switching (on/off). note bits 4 and 5 are read-only bits. remark iice0: bit 7 of iic control register 0 (iicc0)
chapter 11 serial interface function user?s manual u14665ej2v0um 280 (4) iic function expansion register 0 (iicx0) this register sets the function expansion of i 2 c0 (valid only in high-speed mode). iicx0 is set by an 8- or 1-bit memory manipulation instruction. set the clx0 bit in combination with the smc0, dfc0, cl01, and the cl00 bits of iic clock selection register 0 (iiccl0) and the iicce01 and iicce00 bits of iic clock expansion register 0 (iicce0) (see table 11-3 selection clock setting ). reset input sets iicx0 to 00h. after reset: 00h r/w address: fffff34ah 76543210 iicx00000000clx0 (5) iic clock expansion register 0 (iicce0) this register sets the clock selection expansion of i 2 c0. iicce0 is set by an 8-bit memory manipulation instruction. set the iicce01 and iicce00 bits in combination with the smc0, cl01, and cl00 bits of iic clock selection register 0 (iiccl0) and the clx0 bit of iic function expansion register 0 (iicx0) (see table 11-3 selection clock setting ). reset input sets iicce0 to 00h. after reset: 00h r/w address: fffff34ch 76543210 iicce0000000iicce01iicce00 (6) i 2 c0 transfer clock setting method the i 2 c0 transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see table 11-3 selection clock setting .) t: 1/f xx t r : scln rise time t f : scln fall time for example, the i 2 c0 transfer clock frequency (f scl ) when f xx = 16 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using the following expression. f scl = 1/(198 62.5 ns + 200 ns + 50 ns) ? 79.2 khz
chapter 11 serial interface function user?s manual u14665ej2v0um 281 figure 11-7. i 2 c0 transfer clock frequency (f scl ) the selection clock is set using a combination of the smc0, cl01, and cl00 bits of iic clock select register 0 (iiccl0), the clx0 bit of iic function expansion register 0 (iicx0), and the iicce01 and iicce00 bits of iic clock expansion register 0 (iicce0). table 11-3. selection clock setting iicce0 iicx0 iiccl0 bit 1 bit 0 bit 0 bit 3 bit 1 bit 0 iicce01 iicce00 clx0 smc0 cl01 cl00 selection clock (f xx /m) settable main clock frequency (f xx ) range operation mode xx110xf xx /12 4.0 mhz to 4.19 mhz xx010xf xx /24 4.0 mhz to 8.38 mhz xx0110f xx /48 8.0 mhz to 16.0 mhz 010111f xx /36 12.0 mhz to 13.4 mhz 100111f xx /54 16.0 mhz 0 0 0 1 1 1 tm2 output/18 tm2 setting high-speed mode (smc0 = 1) xx0000f xx /44 2.0 mhz to 4.19 mhz xx0001f xx /86 4.19 mhz to 8.38 mhz xx0010f xx /172 8.38 mhz to 16.0 mhz 010011f xx /132 12.0 mhz to 13.4 mhz 100011f xx /198 16.0 mhz 0 0 0 0 1 1 tm2 output/66 tm2 setting other than above setting prohibited normal mode (smc0 = 0) remarks 1. x: don?t care 2. when the selection clock is output from a timer, the p30/to2/ti2 pin does not need to be set in timer output mode. m t + t r + t f m/2 t t f t r m/2 t scln scl0 inversion scl0 inversion scl0 inversion
chapter 11 serial interface function user?s manual u14665ej2v0um 282 (7) iic shift register 0 (iic0) iic0 is used for serial transmission/reception (shift operations) that are synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iic0 during a data transfer. after reset: 00h r/w address: fffff348h 76543210 iic0 (8) slave address register 0 (sva0) sva0 holds the i 2 c bus?s slave addresses. it can be read from or written to in 8-bit units, but bit 0 should be fixed to 0. after reset: 00h r/w address: fffff346h 76543210 sva0 0
chapter 11 serial interface function user?s manual u14665ej2v0um 283 11.3.3 i 2 c bus mode functions (1) pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. scl0 ...............this pin is used for serial clock i/o. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sda0 ..............this pin is used for serial data i/o. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 11-8. pin configuration diagram v dd scl0 sda0 scl0 sda0 v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 11 serial interface function user?s manual u14665ej2v0um 284 11.3.4 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus is shown below. figure 11-9. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. however, in the slave device, scl0?s low- level period can be extended and a wait can be inserted. (1) start condition a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions. figure 11-10. start conditions h scl0 sda0 a start condition is output when bit 1 (stt0) of iic control register 0 (iicc0) is set to 1 after a stop condition has been detected (spd0: bit 0 = 1 in iic status register 0 (iics0)). when a start condition is detected, bit 1 (std0) of iics0 is set to 1.
chapter 11 serial interface function user?s manual u14665ej2v0um 285 (2) addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit data matches the data values stored in slave address register 0 (sva0). if the 7-bit data matches the sva0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 11-11. address address scl0 1 sda0 intiic0 note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note intiic0 is not generated if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in (3) transfer direction specification below, are written together to iic shift register 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0.
chapter 11 serial interface function user?s manual u14665ej2v0um 286 (3) transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 11-12. transfer direction specification scl0 1 sda0 intiic0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note intiic0 is not generated if data other than a local address or extension code is received during slave device operation.
chapter 11 serial interface function user?s manual u14665ej2v0um 287 (4) acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not correctly performed. (b) the final data was received. when the receiving device sets the sda0 line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke0) of iic control register 0 (iicc0) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes bit 3 (trc0) of iic status register 0 (iics0) to be set. when this trc0 bit?s value is 0, it indicates receive mode. therefore, acke0 should be set to 1. when the slave device is receiving (when trc0 = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acke0 to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc0 = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acke0 to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda0 line (i.e., stops transmission) during transmission from the slave device. figure 11-13. ack signal scl0 1 sda0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack
chapter 11 serial interface function user?s manual u14665ej2v0um 288 when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the eighth clock of scl0 regardless of the acke0 value. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: the ack signal is output at the falling edge of the eighth clock of scl0 if acke0 is set to 1 before wait cancellation. when 9-clock wait is selected: the ack signal is automatically output at the falling edge of the eighth clock of scl0 if acke0 has already been set to 1. (5) stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 11-14. stop condition h scl0 sda0 a stop condition is generated when bit 0 (spt0) of iic control register 0 (iicc0) is set to 1. when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is set to 1 and intiic0 is generated when bit 4 (spie0) of iicc0 is set to 1.
chapter 11 serial interface function user?s manual u14665ej2v0um 289 (6) wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when the wait status has been canceled for both the master and slave devices, the next data transfer can begin. figure 11-15. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acke0 = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 or wrel0 is set to 1. transfer lines
chapter 11 serial interface function user?s manual u14665ej2v0um 290 figure 11-15. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acke0 = 1) scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 or wrel0 is set to 1. output according to previously set acke0 value transfer lines remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, when bit 5 (wrel0) of iicc0 is set to 1 or when ffh is written to iic shift register 0 (iic0), the wait status is canceled and the transmitting side writes data to iic0 to cancel the wait status. the master device can also cancel the wait status via either of the following methods. ? by setting bit 1 (stt0) of iicc0 to 1 ? by setting bit 0 (spt0) of iicc0 to 1
chapter 11 serial interface function user?s manual u14665ej2v0um 291 11.3.5 i 2 c interrupt request (intiic0) the following shows the value of iic status register 0 (iics0) at the intiic0 interrupt request generation timing and at the intiic0 interrupt timing. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtim0 = 0 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 10xxx110b  2: iics0 = 10xxx000b  3: iics0 = 10xxx000b (wtim0 = 0)  4: iics0 = 10xxxx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 10xxx110b  2: iics0 = 10xxx100b  3: iics0 = 10xxxx00b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 292 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtim0 = 0 stt0 = 1 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4  5  6 ? 7  1: iics0 = 10xxx110b  2: iics0 = 10xxx000b (wtim0 = 1)  3: iics0 = 10xxxx00b (wtim0 = 0)  4: iics0 = 10xxx110b (wtim0 = 0)  5: iics0 = 10xxx000b (wtim0 = 1)  6: iics0 = 10xxxx00b ? 7: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 stt0 = 1 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 10xxx110b  2: iics0 = 10xxxx00b  3: iics0 = 10xxx110b  4: iics0 = 10xxxx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 293 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim0 = 0 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 1010x110b  2: iics0 = 1010x000b  3: iics0 = 1010x000b (wtim0 = 1)  4: iics0 = 1010xx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 1010x110b  2: iics0 = 1010x100b  3: iics0 = 1010xx00b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 294 (2) slave device operation (when receiving slave address data (matches with sva0)) (a) start ~ address ~ data ~ data ~ stop <1> when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0001x110b  2: iics0 = 0001x000b  3: iics0 = 0001x000b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0001x110b  2: iics0 = 0001x100b  3: iics0 = 0001xx00b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 295 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0001x110b  2: iics0 = 0001x000b  3: iics0 = 0001x110b  4: iics0 = 0001x000b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0001x110b  2: iics0 = 0001xx00b  3: iics0 = 0001x110b  4: iics0 = 0001xx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 296 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0001x110b  2: iics0 = 0001x000b  3: iics0 = 0010x010b  4: iics0 = 0010x000b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4  5 ? 6  1: iics0 = 0001x110b  2: iics0 = 0001xx00b  3: iics0 = 0010x010b  4: iics0 = 0010x110b  5: iics0 = 0010xx00b ? 6: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 297 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 = 0 (after restart, mismatches with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0001x110b  2: iics0 = 0001x000b  3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, mismatches with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0001x110b  2: iics0 = 0001xx00b  3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 298 (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop <1> when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0010x010b  2: iics0 = 0010x000b  3: iics0 = 0010x000b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0010x010b  2: iics0 = 0010x110b  3: iics0 = 0010x100b  4: iics0 = 0010xx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 299 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0010x010b  2: iics0 = 0010x000b  3: iics0 = 0001x110b  4: iics0 = 0001x000b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4  5 ? 6  1: iics0 = 0010x010b  2: iics0 = 0010x110b  3: iics0 = 0010xx00b  4: iics0 = 0001x110b  5: iics0 = 0001xx00b ? 6: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 300 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0010x010b  2: iics0 = 0010x000b  3: iics0 = 0010x010b  4: iics0 = 0010x000b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4  5  6 ? 7  1: iics0 = 0010x010b  2: iics0 = 0010x110b  3: iics0 = 0010xx00b  4: iics0 = 0010x010b  5: iics0 = 0010x110b  6: iics0 = 0010xx00b ? 7: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 301 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 = 0 (after restart, mismatches with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0010x010b  2: iics0 = 0010x000b  3: iics0 = 00000x10b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 (after restart, mismatches with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0010x010b  2: iics0 = 0010x110b  3: iics0 = 0010xx00b  4: iics0 = 00000x10b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 302 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iics0 = 00000001b remark ? : generated only when spie0 = 1 (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data <1> when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0101x110b (example: when ald0 is read during interrupt servicing)  2: iics0 = 0001x000b  3: iics0 = 0001x000b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0101x110b (example: when ald0 is read during interrupt servicing)  2: iics0 = 0001x100b  3: iics0 = 0001xx00b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 303 (b) when arbitration loss occurs during transmission of extension code <1> when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 0110x010b (example: when ald0 is read during interrupt servicing)  2: iics0 = 0010x000b  3: iics0 = 0010x000b ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care <2> when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2  3  4 ? 5  1: iics0 = 0110x010b (example: when ald0 is read during interrupt servicing)  2: iics0 = 0010x110b  3: iics0 = 0010x100b  4: iics0 = 0010xx00b ? 5: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 304 (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1 ? 2  1: iics0 = 01000110b (example: when ald0 is read during interrupt servicing) ? 2: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 (b) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1 ? 2  1: iicsn = 0110x010b (example: when ald0 is read during interrupt servicing) iicc0?s lrel0 is set to 1 via software ? 2: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 305 (c) when arbitration loss occurs during data transfer <1> when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2 ? 3  1: iics0 = 10001110b  2: iics0 = 01000000b (example: when ald0 is read during interrupt servicing) ? 3: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 <2> when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp  1  2 ? 3  1: iics0 = 10001110b  2: iics0 = 01000100b (example: when ald0 is read during interrupt servicing) ? 3: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1
chapter 11 serial interface function user?s manual u14665ej2v0um 306 (d) when loss occurs due to restart condition during data transfer <1> not extension code (example: mismatches with sva0) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp  1  2 ? 3  1: iics0 = 1000x110b  2: iics0 = 01000110b (example: when ald0 is read during interrupt servicing) ? 3: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp  1  2 ? 3  1: iics0 = 1000x110b  2: iics0 = 0110x010b (example: when ald0 is read during interrupt servicing) iicc0?s lrel0 is set to 1 via software ? 3: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care dn = d6 to d0
chapter 11 serial interface function user?s manual u14665ej2v0um 307 (e) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp  1 ? 2  1: iics0 = 1000x110b ? 2: iics0 = 01000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care dn = d6 to d0 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition when wtim0 = 1 stt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 1000x110b  2: iics0 = 1000xx00b  3: iics0 = 01000100b (example: when ald0 is read during interrupt servicing) ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 308 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtim0 = 1 stt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak sp  1  2 ? 3  1: iics0 = 1000x110b  2: iics0 = 1000xx00b ? 3: iics0 = 01000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition when wtim0 = 1 spt0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp  1  2  3 ? 4  1: iics0 = 1000x110b  2: iics0 = 1000xx00b  3: iics0 = 01000000b (example: when ald0 is read during interrupt servicing) ? 4: iics0 = 00000001b remark  : always generated ? : generated only when spie0 = 1 x: don?t care
chapter 11 serial interface function user?s manual u14665ej2v0um 309 11.3.6 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) in iic control register 0 (iicc0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown below. table 11-4. intiic0 generation timing and wait control during slave device operation during master device operation wtim0 address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 98 8 1 9 notes 1, 2 9 note 2 9 note 2 99 9 notes 1. the slave device?s intiic0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is output regardless of the value set to bit 2 (acke0) of iicc0. for a slave device that has received an extension code, intiic0 occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of slave address register 0 (sva0), neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: the interrupt and wait timing are determined regardless of the wtim0 bit. ? master device operation: the interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: the interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: the interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancelation method the four wait cancelation methods are as follows. ? by setting bit 5 (wrel0) of iic control register 0 (iicc0) to 1 ? by writing to the iic shift register 0 (iic0) ? by start condition setting (bit 1 (stt0) of iic control register 0 (iicc0) = 1) ? by stop condition setting (bit 0 (spt0) of iic control register 0 (iicc0) = 1) when an 8-clock wait has been selected (wtim0 = 0), the output level of ack must be determined prior to wait cancelation. (5) stop condition detection intiic0 is generated when a stop condition is detected.
chapter 11 serial interface function user?s manual u14665ej2v0um 310 11.3.7 address match detection method when in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. an interrupt request (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 11.3.8 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 11.3.9 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (exc0) is set for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in slave address register 0 (sva0) is not affected. (2) if 11110xx0 is set to sva0 by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc0 = 1 note ? seven bits of data match: coi0 = 1 note note exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 (lrel0) of iic control register 0 (iicc0) to 1 and the cpu will enter the next communication wait state. table 11-5. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
chapter 11 serial interface function user?s manual u14665ej2v0um 311 11.3.10 arbitration when several master devices simultaneously output a start condition (when stt0 is set to 1 before std0 is set to 1 note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald0) in iic status register 0 (iics0) is set via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 11.3.5 i 2 c interrupt request (intiic0) . note std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0)
chapter 11 serial interface function user?s manual u14665ej2v0um 312 figure 11-16. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z table 11-6. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data transmission when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spie0 = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spie0 = 1) note 2 when data is at low level while attempting to output a stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scl0 is at low level while attempting to output a restart condition
chapter 11 serial interface function user?s manual u14665ej2v0um 313 notes 1. when wtim0 (bit 3 of iic control register 0 (iicc0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 5 of iic control register 0 (iicc0) 11.3.11 wakeup function the i 2 c bus slave function is a function that generates an interrupt request (intiic0) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wakeup standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spie0) of iic control register 0 (iicc0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled.
chapter 11 serial interface function user?s manual u14665ej2v0um 314 11.3.12 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to ?1?). if bit 1 (stt0) of iicc0 is set while the bus is not used, a start condition is automatically generated and the wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to iic shift register 0 (iic0) causes the master?s address transfer to start. at this point, bit 4 (spie0) of iicc0 should be set. when stt0 has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been released ............................................. a start condition is generated if the bus has not been released (standby mode) ............. communication reservation to detect which operation mode has been determined for stt0, set stt0, wait for the wait period, then check the msts0 (bit 7 of iic status register 0 (iics0)). wait periods, which should be set via software, are listed in table 11-7. these wait periods can be set via the settings for bits 3, 1, and 0 (smc0, cl01, and cl00) in iic clock selection register 0 (iiccl0). table 11-7. wait periods smc0 cl01 cl00 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 100 101 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks
chapter 11 serial interface function user?s manual u14665ej2v0um 315 the communication reservation timing is shown below. figure 11-17. communication reservation timing 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 =1 communication reservation set std0 output by master with bus access iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected.
chapter 11 serial interface function user?s manual u14665ej2v0um 316 figure 11-18. timing for accepting communication reservations scl0 sda0 std0 spd0 standby mode
chapter 11 serial interface function user?s manual u14665ej2v0um 317 the communication reservation flow chart is illustrated below. figure 11-19. communication reservation flow chart note the communication reservation operation executes a write to iic shift register 0 (iic0) when a stop condition interrupt request occurs. di set1 stt0 define communication reservation wait cancel communication reservation no yes iic0 xxh ei msts0 = 0? (communication reservation) note (generate start condition) ; sets stt0 flag (communication reservation). ; secures wait period set by software (see table 11-7 ). ; confirmation of communication reservation ; clear user flag. ; iic0 write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram).
chapter 11 serial interface function user?s manual u14665ej2v0um 318 11.3.13 cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic clock selection register 0 (iiccl0). (b) set bit 7 (iice0) of iic control register 0 (iicc0). (c) set bit 0 of iicc0.
chapter 11 serial interface function user?s manual u14665ej2v0um 319 11.3.14 communication operations (1) master operations the following is a flow chart of the master operations. figure 11-20. master operation flow chart iiccl0 h select transfer clock. iicc0 h iice0 = spie0 = wtim0= 1 start iic0 write transfer. start iic0 write transfer. wrel0 = 1 start reception. generate stop condition. (no slave with matching address) generate restart condition or stop condition. start data processing data processing acke0 = 0 no yes no no no no no no yes yes yes yes yes intiic0 = 1? wtim0 = 0 acke0 = 1 intiic0 = 1? transfer completed? intiic0 = 1? ackd0 = 1? trc0 = 1? intiic0 = 1? ackd0 = 1? ; stop condition detection ; address transfer completion no (receive) yes (transmit)
chapter 11 serial interface function user?s manual u14665ej2v0um 320 (2) slave operation an example of slave operation is shown below. figure 11-21. slave operation flow chart iicc0 h iice0 = 1 wrel0 = 1 start reception. detect restart condition or stop condition. start acke0 = 0 data processing data processing lrel0 = 1 no yes no no no no no no no yes no yes yes yes yes yes yes wtim0 = 0 acke0 = 1 intiic0 = 1? yes communicate? transfer completed? intiic0 = 1? wtim0 = 1 start iic0 write transfer. intiic0 = 1? exc0 = 1? coi0 = 1? trc0 = 1? ackd0 = 1?
chapter 11 serial interface function user?s manual u14665ej2v0um 321 11.3.15 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer direction and then starts serial communication with the slave device. the shift operation of iic bus shift register 0 (iic0) is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured by iic0 at the rising edge of scl0. the data communication timing is shown below.
chapter 11 serial interface function user?s manual u14665ej2v0um 322 figure 11-22. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 323 figure 11-22. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 324 figure 11-22. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 325 figure 11-23. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l h h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 326 figure 11-23. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 327 figure 11-23. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l h h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) n- ack (when spie0 = 1) note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 11 serial interface function user?s manual u14665ej2v0um 328 11.4 asynchronous serial interface (uart0, uart1) remark n = 0, 1 in section 11.4. uartn has the following two operation modes. (1) operation stopped mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) asynchronous serial interface mode this mode enables full-duplex operation in which one byte of data is transmitted and received after the start bit. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. in addition, a baud rate based on divided clock input to the asckn pin can also be defined. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). 11.4.1 configuration uartn includes the following hardware. table 11-8. configuration of uartn item configuration registers transmit shift registers 0, 1 (txs0, txs1) receive buffer registers 0, 1 (rxb0, rxb1) control registers asynchronous serial interface mode registers 0, 1 (asim0, asim1) asynchronous serial interface status registers 0, 1 (asis0, asis1) baud rate generator control registers 0, 1 (brgc0, brgc1) baud rate generator mode control registers 00, 01 (brgmc00, brgmc01) baud rate generator mode control registers 10, 11 (brgmc10, brgmc11)
chapter 11 serial interface function user?s manual u14665ej2v0um 329 figure 11-24. block diagram of uartn baud rate generator f xx -f xx /2 9 txd0, txd1 asck0, asck1 rxd0, rxd1 intst0, intst1 intsr0, intsr1 0, 1 (rx0, rx1) internal bus selector 0, 1 (txs0, txs1) 8 8 receive shift registers receive buffer registers 0, 1 (rxb0, rxb1) 8 transmit control parity addition receive control parity check transmit shift registers tmx output remark the following indicates the tmx output. when uart0: tm2 when uart1: tm3 (1) transmit shift registers 0, 1 (txs0, txs1) txsn is the register for setting transmit data. data written to txsn is transmitted as serial data. when the data length is set as 7 bits, bit 0 to bit 6 of the data written to txsn is transmitted as serial data. writing data to txsn starts the transmit operation. txsn can be written to by an 8-bit memory manipulation instruction. it cannot be read. reset input sets these registers to ffh. caution do not write to txsn during a transmit operation. (2) receive shift registers 0, 1 (rx0, rx1) rxn register converts serial data input via the rxd0, rxd1 pins to parallel data. when one byte of data is received at rxn, the received data is transferred to receive buffer registers 0, 1(rxb0, rxb1). rx0, rx1 cannot be manipulated directly by a program.
chapter 11 serial interface function user?s manual u14665ej2v0um 330 (3) receive buffer registers 0, 1 (rxb0, rxb1) rxbn is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred. when the data length is set as 7 bits, received data is sent to bit 0 to bit 6 of rxbn. in rxbn, the msb must be set to ?0?. rxbn can be read by an 8-bit memory manipulation instruction. it cannot be written. reset input sets rxbn to ffh. (4) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (txsn), based on the values set to asynchronous serial interface mode register n (asimn). (5) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register n (asimn). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register n (asisn) according to the type of error that is detected. 11.4.2 uartn control registers uartn is controlled by the following registers. ? asynchronous serial interface mode register n (asimn) ? asynchronous serial interface status register n (asisn) ? baud rate generator control register n (brgcn) ? baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1)
chapter 11 serial interface function user?s manual u14665ej2v0um 331 (1) asynchronous serial interface mode registers 0, 1 (asim0, asim1) asimn is an 8-bit register that controls uartn?s serial transfer operations. asimn can be set by an 8- or 1-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff300h, fffff310h 76543210 asimn txen rxen ps1n ps0n ucln sln isrmn 0 txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stopped port function port function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity ucln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution do not switch the operation mode until after the current serial transmit/receive operation has been stopped.
chapter 11 serial interface function user?s manual u14665ej2v0um 332 (2) asynchronous serial interface status registers 0, 1 (asis0, asis1) when a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. asisn can be read by an 8- or 1-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r address: fffff302h, fffff312h 76543210 asisn 0 0 0 0 0 pen fen oven pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if a stop bit length has been set as two bits by setting bit 2 (sln) in asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data.
chapter 11 serial interface function user?s manual u14665ej2v0um 333 (3) baud rate generator control registers 0, 1 (brgc0, brgc1) these registers set the serial clock for uartn. brgcn can be set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff304h, fffff314h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 selection of input clock k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 ???????? ? ? ???????? ? ? ???????? ? ? 11111111f sck /255 255 cautions 1. the value of brgcn becomes 00h after reset. before starting operation, select a setting other than ?setting prohibited?. selecting the ?setting prohibited? setting in stop mode does not cause any problems. 2. if write is performed to brgcn during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 11 serial interface function user?s manual u14665ej2v0um 334 (4) baud rate generator mode control registers n0, n1 (brgmcn0, brgmcn1) these registers set the uartn source clock. brgmcn0 and brgmcn1 are set by an 8-bit memory manipulation instruction. reset input sets these registers to 00h. after reset: 00h r/w address: fffff30eh, fffff31eh 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 after reset: 00h r/w address: fffff320h, fffff322h 76543210 brgmcn10000000tpsn3 tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0: tm2 output at n = 1: tm3 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? caution if write is performed to brgmcn0, n1 during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. therefore, do not write to brgmcn0, n1 during communication processing. remarks 1. f sck : source clock of 8-bit counter 2. when the selection clock is output from the timer, pins p30/to2/ti2 and p31/to3/ti3 do not need to be set to timer output mode.
chapter 11 serial interface function user?s manual u14665ej2v0um 335 11.4.3 operations uartn has the following two operation modes. ? operation stopped mode ? asynchronous serial interface mode (1) operation stopped mode in this mode, serial transfers are not performed and therefore power consumption can be reduced. when in operation stopped mode, pins can be used as ordinary ports. (a) register settings operation stopped mode settings are made via bits txen and rxen of asynchronous serial interface mode register n (asimn). figure 11-25. asimn setting (operation stopped mode) after reset: 00h r/w address: fffff300h, fffff310h 76543210 asimn txen rxen ps1n ps0n cln sln isrmn 0 txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 0 operation stopped port function port function caution do not switch the operation mode until after the current serial transmit/receive operation has been stopped. (2) asynchronous serial interface mode this mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received. the on-chip dedicated uartn baud rate generator enables communications using a wide range of selectable baud rates. the uartn baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps).
chapter 11 serial interface function user?s manual u14665ej2v0um 336 (a) register settings the asynchronous serial interface mode settings are made via asimn, brgcn, brgmcn0, and brgmcn1. figure 11-26. asimn setting (asynchronous serial interface mode) after reset: 00h r/w address: fffff300h, fffff310h 76543210 asimn txen rxen ps1n ps0n cln sln isrmn 0 txen rxen operation mode rxdn/pxx pin function txdn/pxx pin function 0 1 uartn mode (receive only) serial function port function 1 0 uartn mode (transmit only) port function serial function 1 1 uartn mode (transmit and receive) serial function serial function ps1n ps0n parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cln character length specification 0 7 bits 1 8 bits sln stop bit length specification for transmit data 01 bit 1 2 bits isrmn receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution do not switch the operation mode until after the current serial transmit/receive operation has been stopped.
chapter 11 serial interface function user?s manual u14665ej2v0um 337 figure 11-27. asisn setting (asynchronous serial interface mode) after reset: 00h r address: fffff302h, fffff312h 76543210 asisn 0 0 0 0 0 pen fen oven pen parity error flag 0 no parity error 1 parity error (transmit data parity does not match) fen framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) oven overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes 1. even if the stop bit length has been set as two bits by setting bit 2 (sln) of asynchronous serial interface mode register n (asimn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of receive buffer register n (rxbn) when an overrun error has occurred. until the contents of rxbn are read, further overrun errors will occur when receiving data.
chapter 11 serial interface function user?s manual u14665ej2v0um 338 figure 11-28. brgcn setting (asynchronous serial interface mode) after reset: 00h r/w address: fffff304h, fffff314h 76543210 brgcn mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 input clock selection k 00000 setting prohibited ? 00001000f sck /8 8 00001001f sck /9 9 00001010f sck /10 10 00001011f sck /11 11 00001100f sck /12 12 00001101f sck /13 13 00001110f sck /14 14 00001111f sck /15 15 00010000f sck /16 16 ???????? ? ? ???????? ? ? ???????? ? ? 11111111f sck /255 255 cautions 1. before starting operation, select a setting other than ?setting prohibited?. selecting ?setting prohibited? setting in stop mode does not cause any problems. 2. if write is performed to brgcn during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgcn during communication processing. remark f sck : source clock of 8-bit counter
chapter 11 serial interface function user?s manual u14665ej2v0um 339 figure 11-29. brgmcn0 and brgmcn1 settings (asynchronous serial interface mode) after reset: 00h r/w address: fffff30eh, fffff31eh 76543210 brgmcn0 0 0 0 0 0 tpsn2 tpsn1 tpsn0 after reset: 00h r/w address: fffff320h, fffff322h 76543210 brgmcn10000000tpsn3 tpsn3 tpsn2 tpsn1 tpsn0 8-bit counter source clock selection m 0 0 0 0 external clock (asckn) ? 0001f xx 0 0010f xx /2 1 0011f xx /4 2 0100f xx /8 3 0101f xx /16 4 0110f xx /32 5 0 1 1 1 at n = 0: tm3 output at n = 1: tm2 output ? 1000f xx /64 6 1001f xx /128 7 1010f xx /256 8 1011f xx /512 9 1100 ? 1101 ? 1110 ? 1111 setting prohibited ? caution if write is performed to brgmcn0, n1 during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. therefore, do not write to brgmcn0 and brgmcn1 during communication processing. remarks 1. f xx : main clock oscillation frequency 2. when the selection clock is output from the timer, pins p30/to2/ti2 and p31/to3/ti3 do not need to be set in timer output mode.
chapter 11 serial interface function user?s manual u14665ej2v0um 340 (b) baud rate the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. [baud rate] = [hz] f xx : main clock oscillation frequency m: value set by tpsn3 to tpsn0 (0 m 9) k: value set by mdln7 to mdln0 (8 k 255) ? baud rate tolerance the baud rate tolerance depends on the number of bits in a frame and the counter division ratio [1/(16+k)]. table 11-9 shows the relationship between the main clock and the baud rate, and figure 11-30 shows an example of the baud rate tolerance. table 11-9. relationship between main clock and baud rate f xx = 16 mhz f xx = 8 mhz baud rate (bps) k m error (%) k m error (%) 32 ? ? ? 244 9 0.06 64 244 9 0.06 244 8 0.06 128 244 8 0.06 244 7 0.06 300 208 7 0.16 208 6 0.16 600 208 6 0.16 208 5 0.16 1200 208 5 0.16 208 4 0.16 2400 208 4 0.16 208 3 0.16 4800 208 3 0.16 208 2 0.16 9600 208 2 0.16 208 1 0.16 19200 208 1 0.16 208 0 0.16 38400 208 0 0.16 104 0 0.16 76800 104 0 0.16 52 0 0.16 150000 53 0 0.63 27 0 ?1.24 300000 27 0 ?1.24 13 0 2.56 remark f xx : main clock oscillation frequency f xx 2 m+1 k
chapter 11 serial interface function user?s manual u14665ej2v0um 341 figure 11-30. error tolerance (when k = 16), including sampling errors basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t?) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t remark t: 8-bit counter?s source clock cycle baud rate error tolerance (when k = 16) = 100 = 4.8438 (%) 15.5 320
chapter 11 serial interface function user?s manual u14665ej2v0um 342 (3) communication operations (a) data format as shown in figure 11-31, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. asynchronous serial interface mode register n (asimn) is used to set the character bit length, parity selection, and stop bit length within each data frame. figure 11-31. format of transmit/receive data in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so during a transmission the most significant bit (bit 7) is ignored and during reception the most significant bit (bit 7) must be set to 0. asynchronous serial interface mode register n (asimn) and baud rate generator control register n (brgcn) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register n (asisn).
chapter 11 serial interface function user?s manual u14665ej2v0um 343 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number is set an even number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?1? if the transmit data contains an even number of ?1? bits: the parity bit value is ?0? ? during reception the number of ?1? bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an odd number. (ii) odd parity ? during transmission the number of bits in transmit data including a parity bit is controlled so that the number is set an odd number of ?1? bits. the value of the parity bit is as follows. if the transmit data contains an odd number of ?1? bits: the parity bit value is ?0? if the transmit data contains an even number of ?1? bits: the parity bit value is ?1? ? during reception the number of ?1? bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an even number. (iii) zero parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will be generated regardless of whether the parity bit is a ?0? or a ?1?. (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will be generated.
chapter 11 serial interface function user?s manual u14665ej2v0um 344 (c) transmission a transmit operation is started when transmit data is written to transmit shift register n (txsn). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting a transmit operation shifts out the data in txsn, thereby emptying txsn, after which a transmit completion interrupt (intstn) is issued. the timing of the transmit completion interrupt is shown below. figure 11-32. timing of asynchronous serial interface transmit completion interrupt caution do not write to asynchronous serial interface mode register n (asimn) during a transmit operation. writing to asimn during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intstn) or the interrupt request flag (stifn) that is set by intstn. txdn (output) d0 d1 d2 d6 d7 parity stop start intstn (a) stop bit length: 1 txdn (output) d0 d1 d2 d6 d7 parity start intstn (b) stop bit length: 2 stop
chapter 11 serial interface function user?s manual u14665ej2v0um 345 (d) reception a receive operation is enabled when bit 6 (rxen) of asynchronous serial interface mode register n (asimn) is set to 1, and input via the rxdn pin is sampled. the serial clock specified by asimn is used when sampling the rxdn pin. when the rxdn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxdn pin input with this start timing signal yields a low-level result, the start bit is recognized, after which the 8-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is complete, the receive data in the shift register is transferred to receive buffer register n (rxbn) and a receive completion interrupt (intsrn) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxbn. when an error occurs, instrn is generated if bit 1 (isrmn) of asimn is cleared (0). on the other hand, intsrn is not generated if the isrmn bit is set (1). if the rxen bit is reset to 0 during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxbn and asisn do not change, nor does intsrn or intsern occur. the timing of the asynchronous serial interface receive completion interrupt is shown below. figure 11-33. timing of asynchronous serial interface receive completion interrupt caution be sure to read the contents of receive buffer register n (rxbn) even when a receive error has occurred. if the contents of rxbn are not read, an overrun error will occur during the next data receive operation and the receive error status will remain. rxdn (input) d0 d1 d2 d6 d7 parity stop start intsrn
chapter 11 serial interface function user?s manual u14665ej2v0um 346 (e) receive error there are three types of errors during a receive operation: a parity error, a framing error, and an overrun error. when, as the result of data reception, an error flag is set in asynchronous serial interface status register n (asisn), the receive error interrupt request (intsern) is generated. the receive error interrupt request is generated prior to the receive completion interrupt request (intsrn). by reading the contents of asisn during receive error interrupt servicing (intsern), it is possible to detect which error has occurred at reception. the contents of asisn are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data (if there is an error in the subsequent data, the error flag is set). table 11-10. receive error causes receive error cause asisn value parity error parity specification at transmission and receive data parity do not match. 04h framing error stop bit is not detected. 02h overrun error reception of subsequent data was completed before data was read from the receive buffer register. 01h figure 11-34. receive error timing rxdn (input) intsrn n o t e d7 d6 d2 d1 d0 parity stop start intsern intsern (when parity error occurs) note even if a receive error occurs when the isrmn bit of asimn is set (1), intsrn is not generated. cautions 1. the contents of asynchronous serial interface status register n (asisn) are reset (0) by reading receive buffer register n (rxbn) or receiving subsequent data. to check the contents of an error, always read asisn before reading rxbn. 2. be sure to read receive buffer register n (rxbn) even when a receive error has been generated. if rxbn is not read out, an overrun error will occur during subsequent data reception and as a result receive errors will continue to occur.
chapter 11 serial interface function user?s manual u14665ej2v0um 347 11.4.4 standby function (1) operation in halt mode serial transfer operations are performed normally. (2) operation in stop and idle modes (a) when internal clock is selected as serial clock the operations of asynchronous serial interface mode register n (asimn), transmit shift register n (txsn), and receive buffer register n (rxbn) are stopped and their values immediately before the clock stopped are held. the txdn pin output holds the data immediately before the clock is stopped (in stop mode) during transmission. when the clock is stopped during reception, the receive data until the clock stopped is stored and subsequent receive operations are stopped. reception resumes upon clock restart. (b) when external clock is selected as serial clock serial transfer operations are performed normally.
chapter 11 serial interface function user?s manual u14665ej2v0um 348 11.5 3-wire variable-length serial i/o (csi4) csi4 has the following two operation modes. (1) operation stopped mode this mode is used when serial transfers are not performed. (2) 3-wire variable-length serial i/o mode (msb/lsb first switchable) this mode transfers variable data of 8 to 16 bits via three lines: a serial clock line (sck4), a serial output line (so4), and a serial input line (si4). since data can be transmitted and received simultaneously in 3-wire variable-length serial i/o mode, the processing time of data transfer is shortened. msb and lsb can be switched for the first bit of data to be transferred in serial. 3-wire variable-length serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. caution the serial clock (sck4) must be used within the range of sck4 2.5 mhz. 11.5.1 configuration csi4 includes the following hardware. table 11-11. configuration of csi4 item configuration register variable-length serial io shift register 4 (sio4) control registers variable-length serial control register 4 (csim4) variable-length serial setting register 4 (csib4) baud rate generator source clock selection register 4 (brgcn4) baud rate generator output clock selection register 4 (brgck4)
chapter 11 serial interface function user?s manual u14665ej2v0um 349 figure 11-35. block diagram of 3-wire variable-length serial i/o baud rate generator so4 si4 intcsi4 serial clock controller selector interrupt generator serial clock counter (8-/16-bit switchable) variable length i/o shift register 4 (8/16 bits) sck4 direction controller internal bus (1) variable-length serial i/o shift register 4 (sio4) sio4 is a 16-bit variable register that performs parallel-serial conversion and transmission/reception (shift operations) in synchronization with the serial clock. sio4 is set by a 16-bit memory manipulation instruction. a serial operation starts when data is written to or read from sio4, while bit 7 (csie4) of variable-length serial control register 4 (csim4) is 1. when transmitting, data written to sio4 is output via the serial output (so4). when receiving, data is read from the serial input (si4) and written to sio4. reset input resets sio4 to 0000h. caution do not access sio4 except via the transfer start trigger during a transfer operation (read is disabled when mode4 = 0 and write is disabled when mode4 = 1). after reset: 0000h r/w address: fffff2e0h 1514131211109876543210 sio4
chapter 11 serial interface function user?s manual u14665ej2v0um 350 when the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether msb or lsb is set for the first transfer bit. any data can be set to the unused higher bits, however, in this case the received data after a serial transfer operation becomes 0. figure 11-36. when transfer bit length other than 16 bits is set (a) when transfer bit length is 10 bits and msb first (b) when transfer bit length is 12 bits and lsb first si4 so4 15 10 9 0 fixed to 0 si4 so4 fixed to 0 15 12 11 0
chapter 11 serial interface function user?s manual u14665ej2v0um 351 11.5.2 csi4 control registers csi4 is controlled by the following registers. ? variable-length serial control register 4 (csim4) ? variable-length serial setting register 4 (csib4) ? baud rate generator source clock selection register 4 (brgcn4) ? baud rate generator output clock selection register 4 (brgck4) (1) variable-length serial control register 4 (csim4) this register is used to enable or disable the serial clock, operation modes, and specific operations of serial interface channel 4. csim4 can be set by an 8- or 1-bit memory manipulation instruction. reset input sets csim4 to 00h. after reset: 00h r/w address: fffff2e2h 76543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 transfer operation mode flag operation mode transfer start trigger so4 output 0 transmit/receive mode sio4 write normal output 1 receive-only mode sio4 read port function scl4 clock selection 0 external clock input (sck4) 1 brg (baud rate generator) notes 1. when csie4 = 0 (sio4 operation disabled status), the port function is available for the si4, so4, and sck4 pins. 2. when csie4 = 1 (sio4 operation enabled status), the port function is available for the si4 pin when using the transmit function only and for the so4 pin when using the dedicated receive function. csie4 mode4
chapter 11 serial interface function user?s manual u14665ej2v0um 352 (2) variable-length serial setting register 4 (csib4) csib4 is used to set the operation format of serial interface channel 4. the bit length of a variable register is set by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4. data is transferred msb first while bit 4 (dir) is 1, and is transferred lsb first while dir is 0. csib4 can be set by an 8- or 1-bit memory manipulation instruction. reset input sets csib4 to 00h. after reset : 00h r/w address: fffff2e4h 76543210 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1 msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited
chapter 11 serial interface function user?s manual u14665ej2v0um 353 (3) baud rate generator source clock selection register 4 (brgcn4) brgcn4 can be set by an 8-bit memory manipulation instruction. reset input sets brgcn4 to 00h. after reset : 00h r/w address: fffff2e6h 76543210 brgcn4 0 0 0 0 0 brgn2 brgn1 brgn0 brgn2 brgn1 brgn0 source clock (f sck )m 000f xx 0 001f xx /2 1 010f xx /4 2 011f xx /8 3 100f xx /16 4 101f xx /32 5 110f xx /64 6 111f xx /128 7
chapter 11 serial interface function user?s manual u14665ej2v0um 354 (4) baud rate generator output clock selection register 4 (brgck4) brgck4 is set by an 8-bit memory manipulation instruction. reset input sets brgck4 to 7fh. after reset : 7fh r/w address: fffff2e8h 76543210 brgck4 0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 brgk6 brgk5 brgk4 brgk3 brgk2 brgk1 brgk0 baud rate output clock k 0000000setting prohibited 0 0000001f sck /2 1 0000010f sck /4 2 0000011f sck /6 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1111110f sck /252 126 1111111f sck /254 127 the baud rate transmit/receive clock that is generated is obtained by dividing the main clock. ? generation of baud rate transmit/receive clock using main clock the transmit/receive clock is obtained by dividing the main clock. the following equation is used to obtain the baud rate from the main clock. [baud rate] = [hz] f xx : main clock oscillation frequency m: value set by brgn2 to brgn0 (0 m 7) k: value set by brgk6 to brgk0 (1 k 127) caution do not use the baud rate transmit/receive clock of the variable-length serial i/o (csi4) with a transfer rate higher than the cpu operation clock. if used with a transfer rate higher than the cpu operation clock, transfer cannot be performed correctly. f xx 2 m k 2
chapter 11 serial interface function user?s manual u14665ej2v0um 355 11.5.3 operations csi4 has the following two operation modes. ? operation stopped mode ? 3-wire variable-length serial i/o mode (1) operation stopped mode in this mode, serial transfers are not performed, and therefore power consumption can be reduced. when in operation stopped mode, si4, so4, and sck4 can be used as normal i/o ports. (a) register settings operation stopped mode is set via the csie4 bit of variable-length serial control register 4 (csim4). while csie4 = 0 (sio4 operation stopped state), the pins connected to si4, so4, or sck4 function as port pins. figure 11-37. csim4 setting (operation stopped mode) after reset : 00h r/w address: fffff2e2h 76543210 csim4 csie4 0 0 0 0 mode4 0 scl4 sio4 operation enable/disable specification shift register operation serial counter port 0 operation disabled cleared port function csie4
chapter 11 serial interface function user?s manual u14665ej2v0um 356 (2) 3-wire variable-length serial i/o mode 3-wire variable-length serial i/o mode is useful when connecting to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck4), a serial output line (so4), and a serial input line (si4). (a) register settings 3-wire variable-length serial i/o mode is set using variable-length serial control register 4 (csim4). figure 11-38. csim4 setting (3-wire variable-length serial i/o mode) after reset : 00h r/w address: fffff2e2h 76543210 csim4csie40000mode40scl4 sio4 operation enable/disable specification shift register operation serial counter port 1 operation enabled count operation enabled serial function + port function transfer operation mode flag operation mode transfer start trigger so4 output 0 transmit/receive mode write to sio4 normal output 1 receive-only mode read from sio4 port function scl4 serial clock selection 0 external clock input (sck4) 1 brg (baud rate generator) csie4 mode4
chapter 11 serial interface function user?s manual u14665ej2v0um 357 the bit length of a variable-length register is set by setting bits 3 to 0 (bsel3 to bsel0) of csib4. data is transferred msb first while bit 4 (dir) is 1, and is transferred lsb first while dir is 0. figure 11-39. csib4 setting (3-wire variable-length serial i/o mode) after reset : 00h r/w address: fffff2e4h 76543210 csib4 0 cmode dmode dir bsel3 bsel2 bsel1 bsel0 cmode dmode sck4 active level si4 interrupt timing so4 output timing 0 0 low level rising edge of sck4 falling edge of sck4 0 1 low level falling edge of sck4 rising edge of sck4 1 0 high level falling edge of sck4 rising edge of sck4 1 1 high level rising edge of sck4 falling edge of sck4 dir serial transfer direction 0 lsb first 1msb first bsel3 bsel2 bsel1 bsel0 bit length of serial register 0 0 0 0 16 bits 10008 bits 10019 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited
chapter 11 serial interface function user?s manual u14665ej2v0um 358 (b) communication operations in 3-wire variable-length serial i/o mode, data is transmitted and received in 8- to 16-bit units, and is specified by setting bits 3 to 0 (bsel3 to bsel0) of variable-length serial setting register 4 (csib4). each bit of data is transmitted or received in synchronization with the serial clock. after transfer of all bits is complete, sio4 stops operation automatically and the interrupt request flag (intcsi4) is set. bits 6 and 5 (cmode and dmode) of variable-length serial setting register 4 (csib4) can change the attribute of the serial clock (sck4) and the phases of serial data (si4 and so4). figure 11-40. timing of 3-wire variable-length serial i/o mode sck4 (cmode = 0) sio4 (write) so4 (dmode = 1) intcsi4 sck4 (cmode = 1) so4 (dmode = 0) remark the arrow shows the si4 data fetch timing. when cmode = 0, the serial clock (sck4) stops at a high level while the operation is stopped, and outputs a low level during a data transfer operation. when cmode = 1, on the other hand, sck4 stops at a low level while the operation is stopped and outputs a high level during a data transfer operation. the phases of the so4 output timing and the s14 fetch timing can be shifted half a clock by setting dmode. however, the interrupt signal (intcsi4) is generated at the final edge of the serial clock (sck4), regardless of the setting of csib4.
chapter 11 serial interface function user?s manual u14665ej2v0um 359 (c) transfer start a serial transfer becomes possible when the following two conditions have been satisfied. ? the sio4 operation control bit (csie4) = 1 ? after a serial transfer, the internal serial clock is stopped. serial transfer starts when the following operation is performed after the above two conditions have been satisfied. ? transmit/transmit and receive mode (mode4 = 0) transfer starts when writing to sio4. ? receive-only mode (mode4 = 1) transfer starts when reading from sio4. caution after data has been written to sio4, transfer will not start even if the csie4 bit is set to 1. completion of the final-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (intcsi4). figure 11-41. timing of 3-wire variable-length serial i/o mode (when csib4 = 08h) sck4 (cmode = 0) si4 intcsi4 12345678 transfer end so4 (dmode = 0) msb lsb msb lsb remark csib4 = 08h (cmode = 0, dmode = 0, dir = 0, bsel3 to bsel0 = 1000)
user?s manual u14665ej2v0um 360 chapter 12 a/d converter 12.1 function the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ani0 to ani11). the v850/sf1 supports low-speed conversion and a low-power consumption mode. (1) hardware start conversion is started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 1 (adm1). one analog input channel is selected from ani0 to ani11, and a/d conversion is performed. if a/d conversion has been started by means of a hardware start, conversion stops once it has been completed, and an interrupt request (intad) is generated. if conversion has been started by means of a software start, conversion is performed repeatedly. each time conversion has been completed, intad is generated.
chapter 12 a/d converter user?s manual u14665ej2v0um 361 the block diagram is shown below. figure 12-1. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 adcgnd intad 4 ads3 ads2 ads1 ads0 adcs trg fr2 fr1 fr0 ega1 ega0 adps selector sample & hold circuit adcgnd voltage comparator tap selector adtrg edge detector controller a/d conversion result register (adcr) trigger enable analog input channel specification register (ads) a/d converter mode register 1 (adm1) internal bus iead a/d converter mode register 2 (adm2) successive approximation register (sar) adcv dd
chapter 12 a/d converter user?s manual u14665ej2v0um 362 12.2 configuration the a/d converter includes the following hardware units. table 12-1. configuration of a/d converter item configuration analog input 12 channels (ani0 to ani11) registers successive approximation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read control registers a/d converter mode register 1 (adm1) a/d converter mode register 2 (adm2) analog input channel specification register (ads) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (msb). when the comparison result has been obtained down to the least significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) each time a/d conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register. the higher 10 bits of this register hold the result of the a/d conversion (the lower 6 bits are fixed to 0). this register is read by a 16-bit memory manipulation instruction. reset input sets adcr to 0000h. when using only the higher 8 bits of the result of the a/d conversion, adcrh is read by an 8-bit memory manipulation instruction. reset input sets adcrh to 00h. caution a write operation to a/d converter mode register 1 (adm1) and the analog input channel specification register (ads) may cause the adcr contents to be undefined. after the conversion, read out the conversion result before writing to adm1 and ads. correct conversion results may not be read if the timing is other than the above. (3) sample & hold circuit the sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) series resistor string the series resistor string is connected between adcv dd and adcgnd and generates a voltage for comparison with the analog input signal.
chapter 12 a/d converter user?s manual u14665ej2v0um 363 (6) ani0 to ani11 pins these are analog input pins for the 12 channels of the a/d converter, and are used to input the analog signals to be converted into digital signals. pins other than ones selected for analog input using the analog input channel specification register (ads) can be used as input ports. caution make sure that the voltages input to ani0 through ani11 do not exceed the rated values. if a voltage higher than adcv dd or lower than adcgnd (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel becomes undefined, and the conversion values of the other channels may also be affected. (7) adcgnd pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the gnd0 pin even when the a/d converter is not in use. (8) adcv dd pin this is the analog power supply pin of the a/d converter. always make the potential at this pin the same as that at the v dd0 pin even when the a/d converter is not in use.
chapter 12 a/d converter user?s manual u14665ej2v0um 364 12.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode register 1 (adm1) ? analog input channel specification register (ads) ? a/d converter mode register 2 (adm2) (1) a/d converter mode register 1 (adm1) this register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. adm1 is set by an 8- or 1-bit memory manipulation instruction. reset input sets adm1 to 00h. (1/2) after reset: 00h r/w address: fffff3c0h 76543210 adm1 adcs trg fr2 fr1 fr0 ega1 ega0 adps adcs a/d conversion control 0 conversion stopped 1 conversion enabled trg software start or hardware start selection 0 software start 1 hardware start
chapter 12 a/d converter user?s manual u14665ej2v0um 365 (2/2) after reset: 00h r/w address: fffff3c0h 76543210 adm1 adcs trg fr2 fr1 fr0 ega1 ega0 adps selection of conversion time f xx adps fr2 fr1 fr0 conversion time note 1 + stabilization time note 2 16 mhz 8 mhz 0 0 0 0 168/f xx setting prohibited setting prohibited 0 0 0 1 120/f xx 7.5 s setting prohibited 0 0 1 0 84/f xx 5.25 s setting prohibited 0 0 1 1 60/f xx setting prohibited 7.5 s 0 1 0 0 48/f xx setting prohibited 5.25 s 0 1 0 1 36/f xx setting prohibited setting prohibited 0 1 1 0 setting prohibited setting prohibited setting prohibited 0 1 1 1 12/f xx setting prohibited setting prohibited 1 0 0 0 168/f xx + 64/f xx setting prohibited setting prohibited 1 0 0 1 120/f xx + 60/f xx 7.5 + 4.2 s setting prohibited 1 0 1 0 84/f xx + 42/f xx 5.25 + 3.0 s setting prohibited 1 0 1 1 60/f xx + 30/f xx setting prohibited 7.5 + 4.2 s 1 1 0 0 48/f xx + 24/f xx setting prohibited 5.25 + 3.0 s 1 1 0 1 36/f xx + 18/f xx setting prohibited setting prohibited 1 1 1 0 setting prohibited setting prohibited setting prohibited 1 1 1 1 12/f xx + 6/f xx setting prohibited setting prohibited ega1 ega0 valid edge specification for external trigger signal 0 0 no edge detection 0 1 detects at falling edge 1 0 detects at rising edge 1 1 detects at both rising and falling edges adps comparator control while a/d conversion is stopped (adcs = 0) 0 comparator on 1 comparator off notes 1. conversion time (actual a/d conversion time). always set the time to 5 s conversion time 10 s. 2. stabilization time (setup time of a/d converter) each a/d conversion requires ?conversion time + stabilization time?. there is no stabilization time when adps = 0. cautions 1. the a/d converter cannot be used when the operation frequency is 2.4 to 3.6 mhz. 2. cut the current consumption by setting the adps bit to 1 when the adcs bit is set to 0.
chapter 12 a/d converter user?s manual u14665ej2v0um 366 (2) analog input channel specification register (ads) ads specifies the port for inputting the analog voltage to be converted into a digital signal. ads is set by an 8- or 1-bit memory manipulation instruction. reset input sets ads to 00h. after reset: 00h r/w address: fffff3c2h 76543210 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel specification 0000ani0 0001ani1 0010ani2 0011ani3 0100ani4 0101ani5 0110ani6 0111ani7 1000ani8 1001ani9 1010ani10 1011ani11 other than above setting prohibited (3) a/d converter mode register 2 (adm2) adm2 specifies connection/disconnection of adcv dd and the series resistor string. adm2 is set by an 8- or 1-bit memory manipulation instruction. reset input sets adm2 to 00h. after reset: 00h r/w address: fffff3c8h 76543210 adm2 0 0 0 0 0 0 0 iead iead a/d current cut control 0 cut between adcv dd and series resistor string 1 connect between adcv dd and series resistor string
chapter 12 a/d converter user?s manual u14665ej2v0um 367 12.4 operation 12.4.1 basic operation <1> select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ads). <2> the sample & hold circuit samples the voltage input to the selected analog input channel. <3> after sampling for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until it has been converted into a digital signal. <4> set bit 9 of the successive approximation register (sar). the tap selector sets the voltage tap of the series resistor string to (1/2) adcv dd . <5> the voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is greater than (1/2) adcv dd , the msb of the sar remains set. if the analog input voltage is less than (1/2) adcv dd , the msb is reset. <6> next, bit 8 of the sar is automatically set, and the analog input voltage is compared again. depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows: ? bit 9 = 1: (3/4) adcv dd ? bit 9 = 0: (1/4) adcv dd the analog input voltage is compared with one of these voltage taps, and bit 8 of the sar is manipulated as follows depending on the result of the comparison. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage voltage tap: bit 8 = 0 <7> the above steps are repeated until bit 0 of the sar has been manipulated. <8> when comparison of all 10 bits of the sar has been completed, the valid digital value remains in the sar, and the value of the sar is transferred and latched to the a/d conversion result register (adcr). at the same time, an a/d conversion end interrupt request (intad) can be generated. caution the first conversion value immediately after starting the a/d conversion may not satisfy the ratings.
chapter 12 a/d converter user?s manual u14665ej2v0um 368 figure 12-2. basic operation of a/d converter sar adcr intad conversion time sampling time sampling operation of a/d converter a/d conversion undefined conversion result conversion result a/d conversion is successively executed until bit 7 (adcs) of a/d converter mode register 1 (adm1) is reset to 0 by software. if adm1 and the analog input channel specification register (ads) are written during a/d conversion, the conversion is initialized. if adcs is set to 1 at this time, conversion is started from the beginning. reset input sets the a/d conversion result register (adcr) to 0000h.
chapter 12 a/d converter user?s manual u14665ej2v0um 369 12.4.2 input voltage and conversion result the analog voltages input to the analog input pins (ani0 to ani11) and the result of the a/d conversion (contents of the a/d conversion result register (adcr)) are related as follows: adcr = int( 1024 + 0.5) or, (adcr ? 0.5) v in < (adcr + 0.5) int ( ): function that returns integer of value enclosed in parentheses v in : analog input voltage adcv dd : a/d converter reference voltage adcr: value of the a/d conversion result register (adcr) the relationship between the analog input voltage and a/d conversion result is shown below. figure 12-3. relationship between analog input voltage and a/d conversion result 113253 2043 1022 20451023 2047 1 2048 1024 20481024 2048 1024 2048 1024 20481024 2048 0 1 2 3 1021 1022 1023 a/d conversion result (adcr) input voltage/adcv dd v in adcv dd adcv dd 1024 adcv dd 1024
chapter 12 a/d converter user?s manual u14665ej2v0um 370 12.4.3 a/d converter operation mode in this mode one of the analog input channels ani0 to ani11 is selected by the analog input channel specification register (ads) and a/d conversion is executed. a/d conversion can be started in the following two ways. ? hardware start: started by trigger input (adtrg) (rising edge, falling edge, or both rising and falling edges can be specified) ? software start: started by setting a/d converter mode register 1 (adm1) the result of the a/d conversion is stored in the a/d conversion result register (adcr) and an interrupt request signal (intad) is generated at the same time.
chapter 12 a/d converter user?s manual u14665ej2v0um 371 (1) a/d conversion by hardware start a/d conversion is on standby if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1. when an external trigger signal is input, the a/d converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads) into a digital signal. when the a/d conversion has been completed, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/d conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. if data with adcs set to 1 is written to adm during a/d conversion, the conversion under execution is stopped, and the a/d converter stands by until a new external trigger signal is input. if the external trigger signal is input, a/d conversion is executed again from the beginning. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 12-4. a/d conversion by hardware start (with falling edge specified) rewriting ads adcs = 1, trg = 1 rewriting ads adcs = 1, trg = 1 a/d conversion adcr intad anin standby status standby status standby status anin anin anim anim anim anin anin anin anim anim external trigger input signal remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter user?s manual u14665ej2v0um 372 (2) a/d conversion by software start if bit 6 (trg) and bit 7 (adcs) of a/d converter mode register 1 (adm1) are set to 1, the a/d converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ads) into a digital signal. when the a/d conversion has been completed, the result of the conversion is stored in the a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once a/d conversion has been started and completed, the next conversion is started immediately. a/d conversion is repeated until new data is written to ads. if ads is rewritten during a/d conversion, the conversion under execution is stopped, and conversion of the newly selected analog input channel is started. if data with adcs set to 0 is written to adm1 during a/d conversion, the conversion is immediately stopped. figure 12-5. a/d conversion by software start rewriting ads adcs = 1, trg = 0 rewriting ads adcs = 1, trg = 0 adcs = 0 a/d conversion adcr intad anin anin anin anim anim anin anin anim ? ? ? ? ? conversion stopped. conversion result does not remain. stopped remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter user?s manual u14665ej2v0um 373 12.5 low power consumption mode the v850/sf1 features a function that can cut or connect the current between adcv dd and the series resistor string. switching can be performed by setting a/d converter mode register 2 (adm2). when not using the a/d converter, cut off the tap selector (a function to reduce current) from the voltage supply block (adcv dd ) while a/d conversion is stopped (adcs = 0) to cut the current consumption. ? set the adps bit of a/d converter mode register 1 (adm1) to 1. ? set the iead bit of a/d converter mode register 2 (adm2) to 0. when the adps bit is reset to 0 (comparator on), stabilization time (5 s max.) is required before starting a/d conversion. therefore, secure a wait of at least 5 s by software. 12.6 cautions (1) current consumption in standby mode the a/d converter stops operation in the stop and idle modes (it can be operated in the halt mode). at this time, the current consumption of the a/d converter can be reduced by stopping the conversion (by resetting bit 7 (adcs) of a/d converter mode register 1 (adm1) to 0). (2) input range of ani0 to ani11 keep the input voltage of the ani0 through ani11 pins to within the rated range. if a voltage greater than adcv dd or lower than adcgnd (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the channel becomes undefined. moreover, the values of the other channels may also be affected. (3) conflict <1> conflict between writing a/d conversion result register (adcr) and reading adcr at end of conversion reading adcr takes precedence. after adcr has been read, a new conversion result is written to adcr. <2> conflict between writing adcr and external trigger signal input at end of conversion the external trigger signal is not input during a/d conversion. therefore, the external trigger signal is not accepted while writing adcr. <3> conflict between writing of adcr and writing a/d converter mode register 1 (adm1) or analog input channel specification register (ads) when adm1 or ads is written immediately after adcr is written following the end of a/d conversion, the conversion result is written to the adcr register, but the timing is such that intad is not generated.
chapter 12 a/d converter user?s manual u14665ej2v0um 374 (4) countermeasures against noise to keep the resolution of 10 bits, prevent noise from being superimposed on the ani0 to ani11 pins. the higher the output impedance of the analog input source, the heavier the influence of noise. to lower noise, connecting an external capacitor as shown in figure 12-6 is recommended. figure 12-6. handling of analog input pin adcv dd v dd0 gnd0 adcgnd clamp with diode with a low v f (0.3 v max.) if noise higher than adcv dd or lower than adcgnd may be generated. c = 100 to 1000 pf (5) ani0 to ani11 the analog input (ani0 to ani11) pins are also used as port pins. to execute a/d conversion with any of ani0 to ani11 selected, do not execute an instruction that inputs data to a port during conversion; otherwise, the resolution may drop. if a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected a/d conversion result may not be obtained because of the influence of coupling noise. therefore, do not apply a pulse to adjacent pins.
chapter 12 a/d converter user?s manual u14665ej2v0um 375 (6) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the analog input channel specification register (ads) are changed. if the analog input pin is changed during conversion, therefore, the result of the a/d conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ads is rewritten. if adif is read immediately after ads has been rewritten, it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet. when stopping a/d conversion and then resuming, clear adif before resuming conversion. figure 12-7. a/d conversion end interrupt generation timing rewriting ads (anin conversion starts) rewriting ads (anim conversion starts) adif is set but conversion of anim is not completed. a/d conversion adcr intad anin anin anim anim anim anin anin anim remarks 1. n = 0, 1, ..., 11 2. m = 0, 1, ..., 11
chapter 12 a/d converter user?s manual u14665ej2v0um 376 (7) adcv dd pin the adcv dd pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ani0 to ani11. even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the v dd0 pin to the adcv dd pin as shown in figure 12-8. figure 12-8. handling of adcv dd pin v dd0 gnd0 adcv dd adcgnd main power supply back-up capacitor (8) reading a/d converter result register (adcr) writing to a/d converter mode register 1 (adm1) and analog input channel specification register (ads) may cause the adcr contents to be undefined. after the conversion, read out the conversion result before writing to adm1 and ads. incorrect conversion results may be read out at timings other than the above.
user?s manual u14665ej2v0um 377 chapter 13 dma functions 13.1 functions the dma (direct memory access) controller transfers data between memory and peripheral i/os based on dma requests sent from on-chip peripheral hardware (such as a serial interface, timer, or a/d converter). this product includes six independent dma channels that can transfer data in 8-bit and 16-bit units. the maximum number of transfers is 256 (when transferring data in 8-bit units). after a dma transfer has occurred a specified number of times, dma transfer completion interrupt (intdma0 to intdma5) requests are output individually from the various channels. the priority levels of the dma channels are fixed as follows for simultaneous generation of multiple dma transfer requests. dma0 > dma1 > dma2 > dma3 > dma4 > dma5 13.2 transfer completion interrupt request after a dma transfer has occurred a specified number of times and the tcn bit in corresponding dma channel control registers 0 to 5 (dchc0 to dchc5) has been set to 1, a dma transfer completion interrupt request (intdma0 to intdma5) to the interrupt controller occurs in each channel. 13.3 control registers remark n = 0 to 5 in section 13.3. 13.3.1 dma peripheral i/o address registers 0 to 5 (dioa0 to dioa5) these registers are used to set the peripheral i/o register address for dma channel n. these registers can be read/written in 16-bit units. after reset: undefined r/w address: dioa0 fffff180h dioa3 fffff1b0h dioa1 fffff190h dioa4 fffff1c0h dioa2 fffff1a0h dioa5 fffff1d0h 15 14 13 12 11 10 9 1 0 dioan 000000 ioan9 to ioan1 0 caution the following peripheral i/o registers must not be set. p4, p5, p6, p9, p11, pm4, pm5, pm6, pm9, pm11, mm, dwc, bcc, psc, pcc, sys, prcmd, dioan, dran, dbcn, dchcn, corcn, corrq, coradn, interrupt control register (xxicn), ispr, pocs, vm45, fcan register (see chapter 18)
chapter 13 dma functions user?s manual u14665ej2v0um 378 13.3.2 dma internal ram address registers 0 to 5 (dra0 to dra5) these registers set dma channel n internal ram addresses. an address is incremented after each transfer is completed, when the dadn bit of the dchcn register is 0. the incrementation value is ?1? for 8-bit transfer and ?2? for 16-bit transfer. these registers can be read/written in 16-bit units. after reset: undefined r/w address: dra0 fffff182h dra3 fffff1b2h dra1 fffff192h dra4 fffff1c2h dra2 fffff1a2h dra5 fffff1d2h 15 14 13 0 dran 00 ran13 to ran0 figure 13-1. correspondence between dran setting value and internal ram xxffffffh xxffb000h xxffafffh xxfff000h xxffefffh xxff8000h xxff7fffh access-prohibited area expansion rom area internal peripheral i/o area internal ram area (dran setting value) (2fffh) (3000h) (3fffh) xxffc000h xxffbfffh (0000h) 16 kb (usable for dma) caution do not set odd addresses for 16-bit transfer (dchcn register dsn = 1). remark the dran register setting values are in parentheses.
chapter 13 dma functions user?s manual u14665ej2v0um 379 379 13.3.3 dma byte count registers 0 to 5 (dbc0 to dbc5) these are 8-bit registers that are used to set the number of transfers for dma channel n. the remaining number of transfers is retained during dma transfer. a value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer. transfer ends when a borrow operation occurs. accordingly, ?number of transfers ? 1? should be set for byte (8-bit) transfers and ?(number of transfers ? 1) 2? should be set for 16-bit transfers. these registers can be read/written in 8-bit units. after reset: undefined r/w address: dbc0 fffff184h dbc3 fffff1b4h dbc1 fffff194h dbc4 fffff1c4h dbc2 fffff1a4h dbc5 fffff1d4h 76543210 dbcn bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 caution values set to bit 0 are ignored during 16-bit transfer. 13.3.4 dma start factor expansion register (dmas) this is an 8-bit register for expanding the factors that start dma. the dma start factor is decided according to the combination of ttypn1 and ttypn0 of the dchcn register. for setting bits dmas2 to dmas0, refer to 13.3.6 start factor settings . this register can be read/written in 8- or 1-bit units. after reset: 00h r/w address: fffff38eh 76543210 dmas 0 0 0 0 0 dmas2 dmas1 dmas0
chapter 13 dma functions user?s manual u14665ej2v0um 380 13.3.5 dma channel control registers 0 to 5 (dchc0 to dchc5) these registers are used to control the dma transfer operation mode for dma channel n. refer to 13.3.6 start factor settings for the ttypn1 and ttypn0 bit settings. these registers can be read/written in 8- or 1-bit units. after reset: 00h r/w address: dchc0 fffff186h dchc3 fffff1b6h dchc1 fffff196h dchc4 fffff1c6h dchc2 fffff1a6h dchc5 fffff1d6h 76543210 dchcn tcn 0 ddadn ttypn1 ttypn0 tdirn dsn enn tcn dma transfer completed/not completed note 1 0 not completed 1 completed ddadn internal ram address count direction control 0 incremented 1 address is fixed tdirn transfer direction control between peripheral i/os and internal ram note 2 0 from internal ram to peripheral i/os 1 from peripheral i/os to internal ram dsn control of transfer data size for dma transfer note 2 0 8-bit transfer 1 16-bit transfer enn control of dma transfer enable/disable status note 3 0 disabled 1 enabled (reset to 0 after dma transfer is complete) notes 1. tcn (n = 0 to 5) is set to 1 when a specified number of transfers are complete, and is cleared to 0 when a write instruction is executed. 2. make sure that the transfer format conforms to the peripheral i/o register specifications (access- enabled data size, read/write, etc.) for the dma peripheral i/o address register (dioan). 3. after the specified number of transfers is complete, this bit is cleared to 0.
chapter 13 dma functions user?s manual u14665ej2v0um 381 381 13.3.6 start factor settings the dma start factor is set using bits 2 to 0 (dmas2 to dmas0) of the dma start factor expansion register (dmas) in combination with bits 4 and 3 (ttypn1, ttypn0) of dma channel control registers 0 to 5 (dchc0 to dchc5). table 13-1 shows the dma start factor settings. table 13-1. start factor settings channel n dmas2 dmas1 dmas0 ttypn1 ttypn0 dma transfer start factor settings 0 0 intcsi0/intiic0 0 1 intcsi1/intsr0 10intad 0xxx 1 1 inttm00 0 0 0 intcsi0/intiic0 1 0 0 intcsi1/intsr0 0 1 intst0 10intp0 1xx x 1 1 inttm10 000intcsi4 1 0 0 intcsi3/intsr1 01intp6 1 0 setting prohibited 2x x x 11intad 0 0 0 inttm3 1 0 0 intcsi3/intsr1 0 1 inttm5 1 0 setting prohibited 3 x xx 1 1 inttm4 0 0 intst1 01intcsi4 10intad 4xxx 1 1 inttm2 0 0 intcsi3/intsr1 01intcsi4 1 0 inttm70 5xxx 1 1 inttm6 remarks 1. dmas2 to dmas0: bits 2 to 0 of the dma start factor expansion register (dmas) 2. ttypn1, ttypn0: bits 4 and 3 of dma channel control register n (dchcn) 3. x: don?t care
382 user?s manual u14665ej2v0um chapter 14 reset function 14.1 general when a low-level input occurs at the reset pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. in addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subsystem clock continues. when the input at the reset pin changes from low level to high level, the reset status is canceled and the cpu resumes program execution. the contents of the various registers should be initialized within the program as necessary. an on-chip noise eliminator uses analog delay to prevent noise-related malfunction at the reset pin. 14.2 pin operations during the system reset period, almost all pins are set to high impedance (except for reset, x2, cpureg, v dd0 , adcv dd , adcgnd, portv dd , portgnd, gnd0, gnd1, gnd2, and v pp /ic). accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor at each pin. if such a resistor is not attached, high impedance will be set for these pins, which could damage the data in memory devices. likewise, make sure the pins are handled so as to prevent such effects at the signal outputs of on- chip peripheral i/o functions and output ports. figure 14-1. system reset timing analog delay eliminated as noise hi-z x1 analog delay 131 ms (@ 16 mhz operation) reset internal system reset signal reset is acknowledged reset is canceled oscillation stabilization time analog delay
chapter 14 reset function user?s manual u14665ej2v0um 383 14.3 power-on-clear operation the v850/sf1 includes a power-on-clear circuit (poc), through which low-voltage detection and v dd0 pin voltage detection (4.2 0.3 v) can be performed using the poc status register (pocs). (1) poc status register (pocs) when a power-on-clear is generated, bit 0 of the pocs register is set to 1. in addition, if the voltage level at the v dd0 pin is less than 4.2 0.3 v, bit 1 of the pocs register is set to 1, thus enabling detection of a voltage level of less than 4.2 0.3 v at the v dd0 pin. in the case of a reset generated by the reset pin, however, the pocm and vm45 bits retain their previous statuses. a low voltage state can be detected by reading the pocs register following reset cancelation. the pocs register is read-only, using an 8-bit memory manipulation instruction. this register is reset when read. after reset: retained note r address: fffff07ah 76543210 pocs000000vm45pocm pocm detection of power-on-clear generation status 0 power-on-clear not generated 1 power-on-clear reset generated vm45 detection of v dd0 pin voltage level 0v dd0 pin voltage of less than 4.5 v not detected 1v dd0 pin voltage of less than 4.5 v detected note this value is 03h only after a power-on-clear reset; it is not initialized by a reset from the reset pin.
chapter 14 reset function user?s manual u14665ej2v0um 384 (2) vm45 control register (vm45c) the detection status (detected/undetected) according to the pocs register?s vm45 bit can be output (monitored) at the vm45/p34 pin via control by the vm45c register. after reset: 00h r/w address: fffff07ch 76543210 pocs 0 0 0 0 0 0 vm45c1 vm45c0 vm45c1 vm45 (v dd0 4.5 v monitor) output enabled/disabled 0 vm45 output at vm45/p34 pin disabled (port function) 1 vm45 output at vm45/p34 pin enabled note vm45c0 vm45 (v dd0 4.5 v monitor) output selection 0 high-level output when vm45 detected 1 low-level output when vm45 detected note when using p34 as an alternate function pin, it is necessary to set the pm34 bit of the port 3 mode register (pm3) to 0 (output mode), or the p34 bit of port 3 (p3) to 0 (0 output).
user?s manual u14665ej2v0um 385 chapter 15 regulator 15.1 outline the v850/sf1 incorporates a regulator to realize a 5 v single power supply, low power consumption, and to reduce noise. this regulator supplies a voltage obtained by stepping down the v dd power supply voltage to oscillation blocks and on-chip logic circuits (excluding the a/d converter and output buffers). the regulator output voltage is set to 3.0 v. refer to 2.4 pin i/o circuit types, i/o buffer power supply and connection of unused pins for the power supply corresponding to each pin. figure 15-1. regulator portv dd -system i/o buffer 3.0 v to 5.5 v (t.b.d.) internal digital circuit (3.0 v) flash memory bidirectional level shifter regulator main/sub oscillators a/d converter 4.5 v to 5.5 v adcv dd portv dd v dd0 cpureg v pp 1 f (recommended) 15.2 operation the regulator of the v850/sf1 operates in every mode (stop, idle, halt). for stabilization of regulator outputs, connect an electrolytic capacitor of about 1 f to the cpureg pin.
user?s manual u14665ej2v0um 386 chapter 16 rom correction function remark n = 0 to 3 in chapter 16. 16.1 general the rom correction function provided in the v850/sf1 is a function that replaces part of a program in the mask rom with a program in the internal ram. first, the instruction of the address where the program replacement should start is replaced with the jmp r0 instruction and the program is instructed to jump to 00000000h. the correction request register (corrq) is then checked. at this time, if the corrqn flag is set (1), program control shifts to the internal ram after being made to jump to the internal ram area by an instruction such as a jump instruction. instruction bugs found in the mask rom can be avoided, and program flow can be changed by using the rom correction function. up to four correction addresses can be specified. cautions 1. the rom correction function cannot be used for the data in the internal rom; it can only be used for instruction codes. if the rom correction is carried out on data, that data will replace the instruction code of the jmp r0 instruction. 2. rom correction for instructions that access the corcn, corrq, or corad0 to corad3 registers is prohibited. figure 16-1. block diagram of rom correction rom (1 mb area) instruction address bus s q r correction address register n (coradn) comparator correction control register (corcnn bit) jmp r0 instruction generation instruction replacement instruction data bus correction request register (corrqn bit) 0 clear instruction
chapter 16 rom correction function user?s manual u14665ej2v0um 387 16.2 rom correction peripheral i/o registers 16.2.1 correction control register (corcn) corcn controls whether or not the instruction of the correction address is replaced with the jmp r0 instruction when the correction address matches the fetch address. whether match detection by a comparator is enabled or disabled can be set for each channel. corcn can be set by an 8- or 1-bit memory manipulation instruction. after reset: 00h r/w address: fffff36ch 76543210 corcn 0 0 0 0 coren3 coren2 coren1 coren0 corenn coradn register and fetch address match detection control 0 match detection disabled 1 match detection enabled
chapter 16 rom correction function 388 user?s manual u14665ej2v0um 16.2.2 correction request register (corrq) corrq saves the channel in which rom correction occurred. the jmp r0 instruction makes the program jump to 00000000h after the correction address matches the fetch address. at this time, the program can judge the following cases by reading corrq. ? reset input: corrq = 00h ? rom correction generation: corrqn bit = 1 ? branch to 00000000h by user program: corrq = 00h after reset: 00h r/w address: fffff36eh 76543210 corrq 0 0 0 0 corrq3 corrq2 corrq1 corrq0 corrqn channel n rom correction request flag 0 no rom correction request occurred. 1 rom correction request occurred. 16.2.3 correction address registers 0 to 3 (corad0 to corad3) coradn sets the start address of an instruction to be corrected (correction address) in the rom. up to four points of the program can be corrected at once since the v850/sf1 has four correction address registers (coradn). set 00000000h to 0003fffeh since the v850/sf1 incorporates a 256 kb rom. bits 0 and 18 to 31 should be fixed to 0. after reset: 00000000h r/w address: corad0: fffff370h corad2: fffff378h corad1: fffff374h corad3: fffff37ch 31 18 17 1 0 coradn fixed to 0 correction address 0
chapter 16 rom correction function user?s manual u14665ej2v0um 389 figure 16-2. rom correction operation and program flow start(reset vector) correction address? corenn = 1? corrqn = 0? yes no data for rom correction setting is loaded from an external memory into the internal ram to initialize rom correction function. if there is a correction code, it is loaded in the internal ram. microcontroller initialization clears corrqn flag. jmp channel n correct code address executes internal rom program executes correction program code jumps to internal rom yes no yes no corrqn flag set jmp r0 the address of the internal ram that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal rom. : executed by a program stored in the internal rom : executed by a program stored in the internal ram : executed by the rom correction function caution check the rom correction generation from the vector table with a high interrupt level when executing rom correction during a vector interrupt routine. if an interrupt conflicts with rom correction, processing is branched to an interrupt vector, where, if rom correction is being re-executed, corrqn is set (1) again and multiple corrqn flags are set (1). the channel for which rom correction is to be executed is determined by the interrupt level.
user?s manual u14665ej2v0um 390 chapter 17 flash memory ( pd70f3079y) the pd70f3079y is the flash memory version of the v850/sf1 and incorporates a 256 kb flash memory. in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock in the same way as in the mask rom version. caution there are differences in noise immunity and noise radiation between flash memory versions and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (cs) (not engineering samples (es)) of the mask rom versions. writing to flash memory can be performed with memory mounted on the target system (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered the development environment and applications in which flash memory is used. ? software can be altered after the v850/sf1 is solder-mounted on the target system. ? small scale production of various models is made easier by differentiating software. ? data adjustment in starting mass production is made easier. 17.1 features ? 4-byte/1-clock access (in instruction fetch access) ? all area batch erase/area unit erase ? communication via serial interface with the dedicated flash programmer ? erase/write voltage: v pp = 7.8 v ? on-board programming ? flash memory programming via self-rewrite in area (128 kb) units is possible 17.1.1 erasing unit this product has following two erasure units. (a) all area batch erase the area of xx000000h to xx03ffffh can be erased at the same time. the erasure time is 4.0 s. (b) area erase erasure can be performed in area units (there are two 128 kb unit areas). the erasure time is 2.0 s for each area. area 0: the area of xx000000h to xx01ffffh (128 kb) is erased area 1: the area of xx020000h to xx03ffffh (128 kb) is erased
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 391 17.1.2 write/read time the write/read time is shown below. write time: 20 s/byte read time: 62.5 ns (cycle time) 17.2 writing with flash programmer writing can be performed either on-board or off-board with the dedicated flash programmer. (1) on-board programming the contents of the flash memory are rewritten after the v850/sf1 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to flash memory is performed by the dedicated program adapter (fa series), etc., before mounting the v850/sf1 on the target system. remark the fa series is a product of naito densei machida mfg. co., ltd. 17.3 programming environment the following shows the environment required for writing programs to the flash memory of the v850/sf1. figure 17-1. environment required for writing programs to flash memory rs-232-c host machine v850/sf1 dedicated flash programmer v ss v pp v dd reset uart/csi a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used as the interface between the dedicated flash programmer and the v850/sf1 to perform writing, erasing, etc. a dedicated program adapter (fa series) required for off-board writing.
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 392 17.4 communication mode communication between the dedicated flash programmer and the v850/sf1 is performed by serial communication using uart0 or csi0 of the v850/sf1. (1) uart0 transfer rate: 4800 to 76800 bps figure 17-2. communication with dedicated flash programmer (uart0) v850/sf1 reset gnd0 to gnd2 v dd0 v pp dedicated flash programmer txd0 rxd0 v pp v dd gnd reset r x d t x d (2) csi0 serial clock: up to 1 mhz (msb first) figure 17-3. communication with dedicated flash programmer (csi0) v850/sf1 reset gnd0 to gnd2 v dd0 v pp dedicated flash programmer so0 si0 v pp v dd gnd reset si so sck0 sck
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 393 (3) csi0 + + + + hs serial clock: up to 1 mhz (msb first) figure 17-4. communication with dedicated flash programmer (csi0 + + + + hs) v850/sf1 reset gnd0 to gnd2 v dd0 v pp dedicated flash programmer so0 si0 v pp v dd gnd reset si so sck0 sck p15 hs the dedicated flash programmer outputs the transfer clock, and the v850/sf1 operates as a slave. when the pg-fp3 is used as the dedicated flash programmer, it generates the following signals to the v850/sf1. for the details, refer to the pg-fp3 manual. table 17-1. signal generation of dedicated flash programmer (pg-fp3) pg-fp3 v850/sf1 measures when connected signal name i/o pin function pin name csi0 uart0 csi0 + hs v pp output writing voltage v pp v dd i/o v dd voltage generation/ voltage monitoring v dd0 gnd ? ground gnd0 to gnd2 clk note output clock output to v850/sf1 x1 reset output reset signal reset si/rxd input receive signal so0/txd0 so/txd output transmit signal si0/rxd0 sck output transfer clock sck0 hs input handshake signal of csi0 + hs p15 note supply clock on the target board. remark : always connected { : does not need to be connected, if generated on the target board : does not need to be connected
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 394 17.5 pin connection when performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. also, install a function on-board to switch from the normal operation mode to the flash memory programming mode. when switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset. therefore, all the ports become output high-impedance, making pin handling necessary if the external device does not acknowledge the output high-impedance status. 17.5.1 v pp pin in the normal operation mode, 0 v is input to the v pp pin. in the flash memory programming mode, a 7.8 v writing voltage is supplied to the v pp pin. the following shows an example of the connection of the v pp pin. figure 17-5. v pp pin connection example v pp dedicated flash programmer connection pin pull-down resistor ( r vpp ) v850/sf1 17.5.2 serial interface pin the following shows the pins used by each serial interface. table 17-2. pins used by serial interfaces serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, p15 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to the conflict of signals and the malfunction of other devices, etc.
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 395 (1) conflict of signals when connecting the dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to output high-impedance. figure 17-6. conflict of signals (serial interface input pin) v850/sf1 other device output pin conflict of signals input pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. dedicated flash p ro g rammer connection p ins (2) malfunction of other device when connecting dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. figure 17-7. malfunction of other device v850/sf1 pin in the flash memory programming mode, if the signal the v850/sf1 outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin v850/sf1 pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. other device input pin dedicated flash programmer connection pin
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 396 17.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 17-8. conflict of signals (reset pin) reset v850/sf1 reset signal generator output pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. dedicated flash programmer connection pin 17.5.4 port pin (including nmi) when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer become output high-impedance. if problems such as disabling the output high- impedance status should occur in the external devices connected to the port, connect them to v dd0 or gnd0 to gnd2 via resistors. 17.5.5 other signal pins connect x1, x2, xt1, and xt2 in the same status as that in the normal operation mode. 17.5.6 power supply supply the power as follows: v dd0 = portv dd supply the power (adcv dd , adcgnd, gnd0 to gnd2, and portgnd) in the same way as in normal operation mode.
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 397 17.6 programming method 17.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 17-9. procedure for manipulating flash memory supplies reset pulse switch to flash memory programming mode select communication system manipulate flash memory end? no yes end start 17.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash programmer, set the v850/sf1 in the flash memory programming mode. when switching modes, set the v pp pin before canceling reset. when performing on-board writing, switch modes using a jumper, etc.
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 398 figure 17-10. flash memory programming mode v pp reset flash memory programming mode 7.8 v 3 v 0 v 12 ? n v pp operation mode 0 v normal operation mode 7.8 v flash memory programming mode 17.6.3 selection of communication mode in the v850/sf1, a communication mode is selected by inputting pulses (16 pulses max.) to the v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 17-3. list of communication mode v pp pulse communication mode remarks 0 csi0 v850/sf1 performs slave operation, msb first 3csi0 + hs v850/sf1 performs slave operation, msb first 8 uart0 communication rate: 9600 bps (after reset), lsb first others rfu setting prohibited caution when uart is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the v pp pulse. 17.6.4 communication command the v850/sf1 communicates with the dedicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850/sf1 is called a ?command?. the response signal sent from the v850/sf1 to the dedicated flash programmer is called a ?response command?. figure 17-11. communication command v850/sf1 command dedicated flash programmer response command
chapter 17 flash memory ( pd70f3079y) user?s manual u14665ej2v0um 399 the following shows the commands for flash memory control of the v850/sf1. all of these commands are issued from the dedicated flash programmer, and the v850/sf1 performs the various processing corresponding to the commands. table 17-4. flash memory control commands category command name function verify batch verify command compares the contents of the entire memory and the input data. erase batch erase command erases the contents of the entire memory. write back command writes back the contents which is overerased. blank check batch blank check command checks the erase state of the entire memory. data write high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. system setting and control status read out command acquires the status of operations. oscillating frequency setting command sets the oscillating frequency. erasure time setting command sets the erasure time of batch erase. writing time setting command sets the writing time of data write. write back time setting command sets the write back time. baud rate setting command sets the baud rate when using uart. silicon signature command reads outs the silicon signature information. reset command escapes from each state. the v850/sf1 sends back response commands to the commands issued from the dedicated flash programmer. the following shows the response commands the v850/sf1 sends out. table 17-5. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. 17.6.5 resources used the resources used in the flash memory programming mode are all the ffe000h to ffe7ffh area of the internal ram and all the registers. the ffe800h to ffefffh area of the internal ram retains data as long as the power is on. the registers that are initialized by reset are changed to default values.
user?s manual u14665ej2v0um 400 chapter 18 fcan controller the v850/sf1 features an on-chip fcan (full controller area network) controller that complies with can specification ver. 2.0, part b. (the v850/sf1 product line includes the pd703079y and pd70f3079y as two- channel devices and the pd703078y as a single-channel device.) 18.1 overview of functions table 18-1 presents an overview of v850/sf1 functions. table 18-1. overview of functions function description protocol can protocol ver. 2.0, part b (standard and extended frame transmission/reception) baud rate maximum 1 mbps (during 16 mhz clock input) data storage ? allocated to common access-enabled ram area ? ram that is mapped to an unused message byte can be used for cpu processing or other processing mask functions ? four ? global ma sks and local ma sks can be used wit hout distinction message configuration can be declared as transmit message or receive message no. of messages 32 messages message storage method ? storage to receive buffer corresponding to each id ? storage to buffer specified by receive mask function remote reception ? remote frames can be received in either the receive message buffer or the transmit message buffer ? if a remote frame is received by a transmit message buffer, there is a choice between having the remote request processed by the cpu or starting the auto transmit function. remote transmission the remote frame can be sent either by setting the transmit message?s rtr bit (m_ctrln register) or by setting the receive message?s send request. time stamp function a time stamp function can be set for receive messages and transmit messages. diagnostic functions ? read-enabled error counter provided. ? ?valid protocol operation flag? provided for verification of bus connections. ? receive-only mode (with auto baud rate detection) provided. ? diagnostic processing mode provided. low-power mode ? can sleep mode (wake up function using can bus enabled) ? can stop mode (wake up function using can bus disabled) remark n = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 401 18.2 configuration fcan is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec peripheral i/o bus) interface as a means of transmitting and receiving signals. (2) mac (memory access controller) this functional block controls access to the can module within the fcan and to the can ram. (3) can module this functional block is involved in the operation of the can protocol layer and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc.
chapter 18 fcan controller 402 user?s manual u14665ej2v0um figure 18-1. block diagram of fcan note pd703079y and 70f3079y only cautions 1. when p114/cantx1, p115/canrx1, p116/cantx2, p117/canrx2 are used during fcan transmission/reception, they can be used as fcan pin functions (cantx1, canrx1, cantx2, canrx2) by setting the port alternate-function control register (pac) (refer to 5.2.10 (2) (b) port alternate-function control register (pac)). 2. when the p114/cantx1 and p116/cantx2 pins are used as cantx1, cantx2, set both the p11 and pm11 registers to 0 (refer to 5.3 setting when port pin is used for alternate function). 3. when the p115/canrx1 and p117/canrx2 pins are used as canrx1 and canrx2, set the p11 register to 0 and the pm11 register to 1. 4. if the fcan register is read/written when the external bus interface function is used, an address/data control signal is output to the external expansion pins (ports 4, 5, 6, 9), so read/write of xxmff800h to xxmfffffh (m = 3, 7, b), which is the fcan address area, should not be performed for the external devices connected to the external expansion pins. 5. if the wait function and idle function are set when the external bus interface function is used, these functions are enabled even reading/writing the fcan register. 6. since no clock is supplied from the subsystem clock to fcan, when stopping the main clock and setting the subsystem clock operation, do not read/write the fcan register. remark n = 1, 2 cantx1 canrx1 cantx2 note canrx2 note cpu fcan controller can ram npb (nec peripheral i/o bus) mac (memory access controller) npb interface can module 1 interrupt request intcen intcrn intctn intcme can module 2 can transceiver 1 can transceiver 2 message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 c1mask0 c1mask1 c1mask2 c1mask3 c2mask0 c2mask1 c2mask2 c2mask3 ... can_h can_l can_h can_l can bus
chapter 18 fcan controller user?s manual u14665ej2v0um 403 18.3 internal registers of fcan controller 18.3.1 configuration of message buffers table 18-2. configuration of message buffers address register name xxnff800h to xxnff81fh message buffer 0 field xxnff820h to xxnff83fh message buffer 1 field xxnff840h to xxnff85fh message buffer 2 field xxnff860h to xxnff87fh message buffer 3 field xxnff880h to xxnff89fh message buffer 4 field xxnff8a0h to xxnff8bfh message buffer 5 field xxnff8c0h to xxnff8dfh message buffer 6 field xxnff8e0h to xxnff8ffh message buffer 7 field xxnff900h to xxnff91fh message buffer 8 field xxnff920h to xxnff93fh message buffer 9 field xxnff940h to xxnff95fh message buffer 10 field xxnff960h to xxnff97fh message buffer 11 field xxnff980h to xxnff99fh message buffer 12 field xxnff9a0h to xxnff9bfh message buffer 13 field xxnff9c0h to xxnff9dfh message buffer 14 field xxnff9e0h to xxnff9ffh message buffer 15 field xxnffa00h to xxnffa1fh message buffer 16 field xxnffa20h to xxnffa3fh message buffer 17 field xxnffa40h to xxnffa5fh message buffer 18 field xxnffa60h to xxnffa7fh message buffer 19 field xxnffa80h to xxnffa9fh message buffer 20 field xxnffaa0h to xxnffabfh message buffer 21 field xxnffac0h to xxnffadfh message buffer 22 field xxnffae0h to xxnffaffh message buffer 23 field xxnffb00h to xxnffb1fh message buffer 24 field xxnffb20h to xxnffb3fh message buffer 25 field xxnffb40h to xxnffb5fh message buffer 26 field xxnffb60h to xxnffb7fh message buffer 27 field xxnffb80h to xxnffb9fh message buffer 28 field xxnffba0h to xxnffbbfh message buffer 29 field xxnffbc0h to xxnffbdfh message buffer 30 field xxnffbe0h to xxnffbffh message buffer 31 field remarks 1. for details of message buffers, see 18.3.2 list of fcan registers . 2. n = 3, 7, b
chapter 18 fcan controller 404 user?s manual u14665ej2v0um 18.3.2 list of fcan registers (1/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff804h can message data length register 00 m_dlc00 xxnff805h can message control register 00 m_ctrl00 xxnff806h can message time stamp register 00 m_time00 xxnff808h can message data register 000 m_data000 xxnff809h can message data register 001 m_data001 xxnff80ah can message data register 002 m_data002 xxnff80bh can message data register 003 m_data003 xxnff80ch can message data register 004 m_data004 xxnff80dh can message data register 005 m_data005 xxnff80eh can message data register 006 m_data006 xxnff80fh can message data register 007 m_data007 xxnff810h can message id register l00 m_idl00 xxnff812h can message id register h00 m_idh00 xxnff814h can message configuration register 00 m_conf00 r/w xxnff815h can message status register 00 m_stat00 r undefined xxnff816h can status set/clear register 00 sc_stat00 w 0000h xxnff824h can message data length register 01 m_dlc01 xxnff825h can message control register 01 m_ctrl01 xxnff826h can message time stamp register 01 m_time01 xxnff828h can message data register 010 m_data010 xxnff829h can message data register 011 m_data011 xxnff82ah can message data register 012 m_data012 xxnff82bh can message data register 013 m_data013 xxnff82ch can message data register 014 m_data014 xxnff82dh can message data register 015 m_data015 xxnff82eh can message data register 016 m_data016 xxnff82fh can message data register 017 m_data017 xxnff830h can message id register l01 m_idl01 xxnff832h can message id register h01 m_idh01 xxnff834h can message configuration register 01 m_conf01 r/w xxnff835h can message status register 01 m_stat01 r undefined xxnff836h can status set/clear register 01 sc_stat01 w 0000h xxnff844h can message data length register 02 m_dlc02 xxnff845h can message control register 02 m_ctrl02 xxnff846h can message time stamp register 02 m_time02 xxnff848h can message data register 020 m_data020 xxnff849h can message data register 021 m_data021 xxnff84ah can message data register 022 m_data022 xxnff84bh can message data register 023 m_data023 xxnff84ch can message data register 024 m_data024 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 405 (2/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff84dh can message data register 025 m_data025 xxnff84eh can message data register 026 m_data026 xxnff84fh can message data register 027 m_data027 xxnff850h can message id register l02 m_idl02 xxnff852h can message id register h02 m_idh02 xxnff854h can message configuration register 02 m_conf02 r/w xxnff855h can message status register 02 m_stat02 r undefined xxnff856h can status set/clear register 02 sc_stat02 w 0000h xxnff864h can message data length register 03 m_dlc03 xxnff865h can message control register 03 m_ctrl03 xxnff866h can message time stamp register 03 m_time03 xxnff868h can message data register 030 m_data030 xxnff869h can message data register 031 m_data031 xxnff86ah can message data register 032 m_data032 xxnff86bh can message data register 033 m_data033 xxnff86ch can message data register 034 m_data034 xxnff86dh can message data register 035 m_data035 xxnff86eh can message data register 036 m_data036 xxnff86fh can message data register 037 m_data037 xxnff870h can message id register l03 m_idl03 xxnff872h can message id register h03 m_idh03 xxnff874h can message configuration register 03 m_conf03 r/w xxnff875h can message status register 03 m_stat03 r undefined xxnff876h can status set/clear register 03 sc_stat03 w 0000h xxnff884h can message data length register 04 m_dlc04 xxnff885h can message control register 04 m_ctrl04 xxnff886h can message time stamp register 04 m_time04 xxnff888h can message data register 040 m_data040 xxnff889h can message data register 041 m_data041 xxnff88ah can message data register 042 m_data042 xxnff88bh can message data register 043 m_data043 xxnff88ch can message data register 044 m_data044 xxnff88dh can message data register 045 m_data045 xxnff88eh can message data register 046 m_data046 xxnff88fh can message data register 047 m_data047 xxnff890h can message id register l04 m_idl04 xxnff892h can message id register h04 m_idh04 xxnff894h can message configuration register 04 m_conf04 r/w xxnff895h can message status register 04 m_stat04 r undefined xxnff896h can status set/clear register 04 sc_stat04 w 0000h xxnff8a4h can message data length register 05 m_dlc05 xxnff8a5h can message control register 05 m_ctrl05 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller 406 user?s manual u14665ej2v0um (3/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff8a6h can message time stamp register 05 m_time05 xxnff8a8h can message data register 050 m_data050 xxnff8a9h can message data register 051 m_data051 xxnff8aah can message data register 052 m_data052 xxnff8abh can message data register 053 m_data053 xxnff8ach can message data register 054 m_data054 xxnff8adh can message data register 055 m_data055 xxnff8aeh can message data register 056 m_data056 xxnff8afh can message data register 057 m_data057 xxnff8b0h can message id register l05 m_idl05 xxnff8b2h can message id register h05 m_idh05 xxnff8b4h can message configuration register 05 m_conf05 r/w xxnff8b5h can message status register 05 m_stat05 r undefined xxnff8b6h can status set/clear register 05 sc_stat05 w 0000h xxnff8c4h can message data length register 06 m_dlc06 xxnff8c5h can message control register 06 m_ctrl06 xxnff8c6h can message time stamp register 06 m_time06 xxnff8c8h can message data register 060 m_data060 xxnff8c9h can message data register 061 m_data061 xxnff8cah can message data register 062 m_data062 xxnff8cbh can message data register 063 m_data063 xxnff8cch can message data register 064 m_data064 xxnff8cdh can message data register 065 m_data065 xxnff8ceh can message data register 066 m_data066 xxnff8cfh can message data register 067 m_data067 xxnff8d0h can message id register l06 m_idl06 xxnff8d2h can message id register h06 m_idh06 xxnff8d4h can message configuration register 06 m_conf06 r/w xxnff8d5h can message status register 06 m_stat06 r undefined xxnff8d6h can status set/clear register 06 sc_stat06 w 0000h xxnff8e4h can message data length register 07 m_dlc07 xxnff8e5h can message control register 07 m_ctrl07 xxnff8e6h can message time stamp register 07 m_time07 xxnff8e8h can message data register 070 m_data070 xxnff8e9h can message data register 071 m_data071 xxnff8eah can message data register 072 m_data072 xxnff8ebh can message data register 073 m_data073 xxnff8ech can message data register 074 m_data074 xxnff8edh can message data register 075 m_data075 xxnff8eeh can message data register 076 m_data076 xxnff8efh can message data register 077 m_data077 xxnff8f0h can message id register l07 m_idl07 xxnff8f2h can message id register h07 m_idh07 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 407 (4/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff8f4h can message configuration register 07 m_conf07 r/w xxnff8f5h can message status register 07 m_stat07 r undefined xxnff8f6h can status set/clear register 07 sc_stat07 w 0000h xxnff904h can message data length register 08 m_dlc08 xxnff905h can message control register 08 m_ctrl08 xxnff906h can message time stamp register 08 m_time08 xxnff908h can message data register 080 m_data080 xxnff909h can message data register 081 m_data081 xxnff90ah can message data register 082 m_data082 xxnff90bh can message data register 083 m_data083 xxnff90ch can message data register 084 m_data084 xxnff90dh can message data register 085 m_data085 xxnff90eh can message data register 086 m_data086 xxnff90fh can message data register 087 m_data087 xxnff910h can message id register l08 m_idl08 xxnff912h can message id register h08 m_idh08 xxnff914h can message configuration register 08 m_conf08 r/w xxnff915h can message status register 08 m_stat08 r undefined xxnff916h can status set/clear register 08 sc_stat08 w 0000h xxnff924h can message data length register 09 m_dlc09 xxnff925h can message control register 09 m_ctrl09 xxnff926h can message time stamp register 09 m_time09 xxnff928h can message data register 090 m_data090 xxnff929h can message data register 091 m_data091 xxnff92ah can message data register 092 m_data092 xxnff92bh can message data register 093 m_data093 xxnff92ch can message data register 094 m_data094 xxnff92dh can message data register 095 m_data095 xxnff92eh can message data register 096 m_data096 xxnff92fh can message data register 097 m_data097 xxnff930h can message id register l09 m_idl09 xxnff932h can message id register h09 m_idh09 xxnff934h can message configuration register 09 m_conf09 r/w xxnff935h can message status register 09 m_stat09 r undefined xxnff936h can status set/clear register 09 sc_stat09 w 0000h xxnff944h can message data length register 10 m_dlc10 xxnff945h can message control register 10 m_ctrl10 xxnff946h can message time stamp register 10 m_time10 xxnff948h can message data register 100 m_data100 xxnff949h can message data register 101 m_data101 xxnff94ah can message data register 102 m_data102 xxnff94bh can message data register 103 m_data103 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller 408 user?s manual u14665ej2v0um (5/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff94ch can message data register 104 m_data104 xxnff94dh can message data register 105 m_data105 xxnff94eh can message data register 106 m_data106 xxnff94fh can message data register 107 m_data107 xxnff950h can message id register l10 m_idl10 xxnff952h can message id register h10 m_idh10 xxnff954h can message configuration register 10 m_conf10 r/w xxnff955h can message status register 10 m_stat10 r undefined xxnff956h can status set/clear register 10 sc_stat10 w 0000h xxnff964h can message data length register 11 m_dlc11 xxnff965h can message control register 11 m_ctrl11 xxnff966h can message time stamp register 11 m_time11 xxnff968h can message data register 110 m_data110 xxnff969h can message data register 111 m_data111 xxnff96ah can message data register 112 m_data112 xxnff96bh can message data register 113 m_data113 xxnff96ch can message data register 114 m_data114 xxnff96dh can message data register 115 m_data115 xxnff96eh can message data register 116 m_data116 xxnff96fh can message data register 117 m_data117 xxnff970h can message id register l11 m_idl11 xxnff972h can message id register h11 m_idh11 xxnff974h can message configuration register 11 m_conf11 r/w xxnff975h can message status register 11 m_stat11 r undefined xxnff976h can status set/clear register 11 sc_stat11 w 0000h xxnff984h can message data length register 12 m_dlc12 xxnff985h can message control register 12 m_ctrl12 xxnff986h can message time stamp register 12 m_time12 xxnff988h can message data register 120 m_data120 xxnff989h can message data register 121 m_data121 xxnff98ah can message data register 122 m_data122 xxnff98bh can message data register 123 m_data123 xxnff98ch can message data register 124 m_data124 xxnff98dh can message data register 125 m_data125 xxnff98eh can message data register 126 m_data126 xxnff98fh can message data register 127 m_data127 xxnff990h can message id register l12 m_idl12 xxnff992h can message id register h12 m_idh12 xxnff994h can message configuration register 12 m_conf12 r/w xxnff995h can message status register 12 m_stat12 r undefined xxnff996h can status set/clear register 12 sc_stat12 w 0000h xxnff9a4h can message data length register 13 m_dlc13 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 409 (6/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff9a5h can message control register 13 m_ctrl13 xxnff9a6h can message time stamp register 13 m_time13 xxnff9a8h can message data register 130 m_data130 xxnff9a9h can message data register 131 m_data131 xxnff9aah can message data register 132 m_data132 xxnff9abh can message data register 133 m_data133 xxnff9ach can message data register 134 m_data134 xxnff9adh can message data register 135 m_data135 xxnff9aeh can message data register 136 m_data136 xxnff9afh can message data register 137 m_data137 xxnff9b0h can message id register l13 m_idl13 xxnff9b2h can message id register h13 m_idh13 xxnff9b4h can message configuration register 13 m_conf13 r/w xxnff9b5h can message status register 13 m_stat13 r undefined xxnff9b6h can status set/clear register 13 sc_stat13 w 0000h xxnff9c4h can message data length register 14 m_dlc14 xxnff9c5h can message control register 14 m_ctrl14 xxnff9c6h can message time stamp register 14 m_time14 xxnff9c8h can message data register 140 m_data140 xxnff9c9h can message data register 141 m_data141 xxnff9cah can message data register 142 m_data142 xxnff9cbh can message data register 143 m_data143 xxnff9cch can message data register 144 m_data144 xxnff9cdh can message data register 145 m_data145 xxnff9ceh can message data register 146 m_data146 xxnff9cfh can message data register 147 m_data147 xxnff9d0h can message id register l14 m_idl14 xxnff9d2h can message id register h14 m_idh14 xxnff9d4h can message configuration register 14 m_conf14 r/w xxnff9d5h can message status register 14 m_stat14 r undefined xxnff9d6h can status set/clear register 14 sc_stat14 w 0000h xxnff9e4h can message data length register 15 m_dlc15 xxnff9e5h can message control register 15 m_ctrl15 xxnff9e6h can message time stamp register 15 m_time15 xxnff9e8h can message data register 150 m_data150 xxnff9e9h can message data register 151 m_data151 xxnff9eah can message data register 152 m_data152 xxnff9ebh can message data register 153 m_data153 xxnff9ech can message data register 154 m_data154 xxnff9edh can message data register 155 m_data155 xxnff9eeh can message data register 156 m_data156 xxnff9efh can message data register 157 m_data157 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller 410 user?s manual u14665ej2v0um (7/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnff9f0h can message id register l15 m_idl15 xxnff9f2h can message id register h15 m_idh15 xxnff9f4h can message configuration register 15 m_conf15 r/w xxnff9f5h can message status register 15 m_stat15 r undefined xxnff9f6h can status set/clear register 15 sc_stat15 w 0000h xxnffa04h can message data length register 16 m_dlc16 xxnffa05h can message control register 16 m_ctrl16 xxnffa06h can message time stamp register 16 m_time16 xxnffa08h can message data register 160 m_data160 xxnffa09h can message data register 161 m_data161 xxnffa0ah can message data register 162 m_data162 xxnffa0bh can message data register 163 m_data163 xxnffa0ch can message data register 164 m_data164 xxnffa0dh can message data register 165 m_data165 xxnffa0eh can message data register 166 m_data166 xxnffa0fh can message data register 167 m_data167 xxnffa10h can message id register l16 m_idl16 xxnffa12h can message id register h16 m_idh16 xxnffa14h can message configuration register 16 m_conf16 r/w xxnffa15h can message status register 16 m_stat16 r undefined xxnffa16h can status set/clear register 16 sc_stat16 w 0000h xxnffa24h can message data length register 17 m_dlc17 xxnffa25h can message control register 17 m_ctrl17 xxnffa26h can message time stamp register 17 m_time17 xxnffa28h can message data register 170 m_data170 xxnffa29h can message data register 171 m_data171 xxnffa2ah can message data register 172 m_data172 xxnffa2bh can message data register 173 m_data173 xxnffa2ch can message data register 174 m_data174 xxnffa2dh can message data register 175 m_data175 xxnffa2eh can message data register 176 m_data176 xxnffa2fh can message data register 177 m_data177 xxnffa30h can message id register l17 m_idl17 xxnffa32h can message id register h17 m_idh17 xxnffa34h can message configuration register 17 m_conf17 r/w xxnffa35h can message status register 17 m_stat17 r undefined xxnffa36h can status set/clear register 17 sc_stat17 w 0000h xxnffa44h can message data length register 18 m_dlc18 xxnffa45h can message control register 18 m_ctrl18 xxnffa46h can message time stamp register 18 m_time18 xxnffa48h can message data register 180 m_data180 xxnffa49h can message data register 181 m_data181 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 411 (8/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffa4ah can message data register 182 m_data182 xxnffa4bh can message data register 183 m_data183 xxnffa4ch can message data register 184 m_data184 xxnffa4dh can message data register 185 m_data185 xxnffa4eh can message data register 186 m_data186 xxnffa4fh can message data register 187 m_data187 xxnffa50h can message id register l18 m_idl18 xxnffa52h can message id register h18 m_idh18 xxnffa54h can message configuration register 18 m_conf18 r/w xxnffa55h can message status register 18 m_stat18 r undefined xxnffa56h can status set/clear register 18 sc_stat18 w 0000h xxnffa64h can message data length register 19 m_dlc19 xxnffa65h can message control register 19 m_ctrl19 xxnffa66h can message time stamp register 19 m_time19 xxnffa68h can message data register 190 m_data190 xxnffa69h can message data register 191 m_data191 xxnffa6ah can message data register 192 m_data192 xxnffa6bh can message data register 193 m_data193 xxnffa6ch can message data register 194 m_data194 xxnffa6dh can message data register 195 m_data195 xxnffa6eh can message data register 196 m_data196 xxnffa6fh can message data register 197 m_data197 xxnffa70h can message id register l19 m_idl19 xxnffa72h can message id register h19 m_idh19 xxnffa74h can message configuration register 19 m_conf19 r/w xxnffa75h can message status register 19 m_stat19 r undefined xxnffa76h can status set/clear register 19 sc_stat19 w 0000h xxnffa84h can message data length register 20 m_dlc20 xxnffa85h can message control register 20 m_ctrl20 xxnffa86h can message time stamp register 20 m_time20 xxnffa88h can message data register 200 m_data200 xxnffa89h can message data register 201 m_data201 xxnffa8ah can message data register 202 m_data202 xxnffa8bh can message data register 203 m_data203 xxnffa8ch can message data register 204 m_data204 xxnffa8dh can message data register 205 m_data205 xxnffa8eh can message data register 206 m_data206 xxnffa8fh can message data register 207 m_data207 xxnffa90h can message id register l20 m_idl20 xxnffa92h can message id register h20 m_idh20 xxnffa94h can message configuration register 20 m_conf20 r/w xxnffa95h can message status register 20 m_stat20 r undefined remark n = 3, 7, b
chapter 18 fcan controller 412 user?s manual u14665ej2v0um (9/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffa96h can status set/clear register 20 sc_stat20 w 0000h xxnffaa4h can message data length register 21 m_dlc21 xxnffaa5h can message control register 21 m_ctrl21 xxnffaa6h can message time stamp register 21 m_time21 xxnffaa8h can message data register 210 m_data210 xxnffaa9h can message data register 211 m_data211 xxnffaaah can message data register 212 m_data212 xxnffaabh can message data register 213 m_data213 xxnffaach can message data register 214 m_data214 xxnffaadh can message data register 215 m_data215 xxnffaaeh can message data register 216 m_data216 xxnffaafh can message data register 217 m_data217 xxnffab0h can message id register l21 m_idl21 xxnffab2h can message id register h21 m_idh21 xxnffab4h can message configuration register 21 m_conf21 r/w xxnffab5h can message status register 21 m_stat21 r undefined xxnffab6h can status set/clear register 21 sc_stat21 w 0000h xxnffac4h can message data length register 22 m_dlc22 xxnffac5h can message control register 22 m_ctrl22 xxnffac6h can message time stamp register 22 m_time22 xxnffac8h can message data register 220 m_data220 xxnffac9h can message data register 221 m_data221 xxnffacah can message data register 222 m_data222 xxnffacbh can message data register 223 m_data223 xxnffacch can message data register 224 m_data224 xxnffacdh can message data register 225 m_data225 xxnffaceh can message data register 226 m_data226 xxnffacfh can message data register 227 m_data227 xxnffad0h can message id register l22 m_idl22 xxnffad2h can message id register h22 m_idh22 xxnffad4h can message configuration register 22 m_conf22 r/w xxnffad5h can message status register 22 m_stat22 r undefined xxnffad6h can status set/clear register 22 sc_stat22 w 0000h xxnffae4h can message data length register 23 m_dlc23 xxnffae5h can message control register 23 m_ctrl23 xxnffae6h can message time stamp register 23 m_time23 xxnffae8h can message data register 230 m_data230 xxnffae9h can message data register 231 m_data231 xxnffaeah can message data register 232 m_data232 xxnffaebh can message data register 233 m_data233 xxnffaech can message data register 234 m_data234 xxnffaedh can message data register 235 m_data235 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 413 (10/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffaeeh can message data register 236 m_data236 xxnffaefh can message data register 237 m_data237 xxnffaf0h can message id register l23 m_idl23 xxnffaf2h can message id register h23 m_idh23 xxnffaf4h can message configuration register 23 m_conf23 r/w xxnffaf5h can message status register 23 m_stat23 r undefined xxnffaf6h can status set/clear register 23 sc_stat23 w 0000h xxnffb04h can message data length register 24 m_dlc24 xxnffb05h can message control register 24 m_ctrl24 xxnffb06h can message time stamp register 24 m_time24 xxnffb08h can message data register 240 m_data240 xxnffb09h can message data register 241 m_data241 xxnffb0ah can message data register 242 m_data242 xxnffb0bh can message data register 243 m_data243 xxnffb0ch can message data register 244 m_data244 xxnffb0dh can message data register 245 m_data245 xxnffb0eh can message data register 246 m_data246 xxnffb0fh can message data register 247 m_data247 xxnffb10h can message id register l24 m_idl24 xxnffb12h can message id register h24 m_idh24 xxnffb14h can message configuration register 24 m_conf24 r/w xxnffb15h can message status register 24 m_stat24 r undefined xxnffb16h can status set/clear register 24 sc_stat24 w 0000h xxnffb24h can message data length register 25 m_dlc25 xxnffb25h can message control register 25 m_ctrl25 xxnffb26h can message time stamp register 25 m_time25 xxnffb28h can message data register 250 m_data250 xxnffb29h can message data register 251 m_data251 xxnffb2ah can message data register 252 m_data252 xxnffb2bh can message data register 253 m_data253 xxnffb2ch can message data register 254 m_data254 xxnffb2dh can message data register 255 m_data255 xxnffb2eh can message data register 256 m_data256 xxnffb2fh can message data register 257 m_data257 xxnffb30h can message id register l25 m_idl25 xxnffb32h can message id register h25 m_idh25 xxnffb34h can message configuration register 25 m_conf25 r/w xxnffb35h can message status register 25 m_stat25 r undefined xxnffb36h can status set/clear register 25 sc_stat25 w 0000h xxnffb44h can message data length register 26 m_dlc26 xxnffb45h can message control register 26 m_ctrl26 xxnffb46h can message time stamp register 26 m_time26 xxnffb48h can message data register 260 m_data260 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller 414 user?s manual u14665ej2v0um (11/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffb49h can message data register 261 m_data261 xxnffb4ah can message data register 262 m_data262 xxnffb4bh can message data register 263 m_data263 xxnffb4ch can message data register 264 m_data264 xxnffb4dh can message data register 265 m_data265 xxnffb4eh can message data register 266 m_data266 xxnffb4fh can message data register 267 m_data267 xxnffb50h can message id register l26 m_idl26 xxnffb52h can message id register h26 m_idh26 xxnffb54h can message configuration register 26 m_conf26 r/w xxnffb55h can message status register 26 m_stat26 r undefined xxnffb56h can status set/clear register 26 sc_stat26 w 0000h xxnffb64h can message data length register 27 m_dlc27 xxnffb65h can message control register 27 m_ctrl27 xxnffb66h can message time stamp register 27 m_time27 xxnffb68h can message data register 270 m_data270 xxnffb69h can message data register 271 m_data271 xxnffb6ah can message data register 272 m_data272 xxnffb6bh can message data register 273 m_data273 xxnffb6ch can message data register 274 m_data274 xxnffb6dh can message data register 275 m_data275 xxnffb6eh can message data register 276 m_data276 xxnffb6fh can message data register 277 m_data277 xxnffb70h can message id register l27 m_idl27 xxnffb72h can message id register h27 m_idh27 xxnffb74h can message configuration register 27 m_conf27 r/w xxnffb75h can message status register 27 m_stat27 r undefined xxnffb76h can status set/clear register 27 sc_stat27 w 0000h xxnffb84h can message data length register 28 m_dlc28 xxnffb85h can message control register 28 m_ctrl28 xxnffb86h can message time stamp register 28 m_time28 xxnffb88h can message data register 280 m_data280 xxnffb89h can message data register 281 m_data281 xxnffb8ah can message data register 282 m_data282 xxnffb8bh can message data register 283 m_data283 xxnffb8ch can message data register 284 m_data284 xxnffb8dh can message data register 285 m_data285 xxnffb8eh can message data register 286 m_data286 xxnffb8fh can message data register 287 m_data287 xxnffb90h can message id register l28 m_idl28 xxnffb92h can message id register h28 m_idh28 xxnffb94h can message configuration register 28 m_conf28 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 415 (12/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffb95h can message status register 28 m_stat28 r undefined xxnffb96h can status set/clear register 28 sc_stat28 w 0000h xxnffba4h can message data length register 29 m_dlc29 xxnffba5h can message control register 29 m_ctrl29 xxnffba6h can message time stamp register 29 m_time29 xxnffba8h can message data register 290 m_data290 xxnffba9h can message data register 291 m_data291 xxnffbaah can message data register 292 m_data292 xxnffbabh can message data register 293 m_data293 xxnffbach can message data register 294 m_data294 xxnffbadh can message data register 295 m_data295 xxnffbaeh can message data register 296 m_data296 xxnffbafh can message data register 297 m_data297 xxnffbb0h can message id register l29 m_idl29 xxnffbb2h can message id register h29 m_idh29 xxnffbb4h can message configuration register 29 m_conf29 r/w xxnffbb5h can message status register 29 m_stat29 r undefined xxnffbb6h can status set/clear register 29 sc_stat29 w 0000h xxnffbc4h can message data length register 30 m_dlc30 xxnffbc5h can message control register 30 m_ctrl30 xxnffbc6h can message time stamp register 30 m_time30 xxnffbc8h can message data register 300 m_data300 xxnffbc9h can message data register 301 m_data301 xxnffbcah can message data register 302 m_data302 xxnffbcbh can message data register 303 m_data303 xxnffbcch can message data register 304 m_data304 xxnffbcdh can message data register 305 m_data305 xxnffbceh can message data register 306 m_data306 xxnffbcfh can message data register 307 m_data307 xxnffbd0h can message id register l30 m_idl30 xxnffbd2h can message id register h30 m_idh30 xxnffbd4h can message configuration register 30 m_conf30 r/w xxnffbd5h can message status register 30 m_stat30 r undefined xxnffbd6h can status set/clear register 30 sc_stat30 w 0000h xxnffbe4h can message data length register 31 m_dlc31 xxnffbe5h can message control register 31 m_ctrl31 xxnffbe6h can message time stamp register 31 m_time31 xxnffbe8h can message data register 310 m_data310 xxnffbe9h can message data register 311 m_data311 xxnffbeah can message data register 312 m_data312 xxnffbebh can message data register 313 m_data313 xxnffbech can message data register 314 m_data314 r/w undefined remark n = 3, 7, b
chapter 18 fcan controller 416 user?s manual u14665ej2v0um (13/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffbedh can message data register 315 m_data315 xxnffbeeh can message data register 316 m_data316 xxnffbefh can message data register 317 m_data317 xxnffbf0h can message id register l31 m_idl31 xxnffbf2h can message id register h31 m_idh31 xxnffbf4h can message configuration register 31 m_conf31 r/w xxnffbf5h can message status register 31 m_stat31 r undefined xxnffbf6h can status set/clear register 31 sc_stat31 w xxnffc00h can interrupt pending register ccintp r 0000h xxnffc02h can global interrupt pending register cgintp xxnffc04h can1 interrupt pending register c1intp xxnffc06h can2 interrupt pending register note 1 c2intp 00h xxnffc0ch can stop register cstop 0000h xxnffc10h can global status register cgst note 2 0100h xxnffc12h can global interrupt enable register cgie note 2 0a00h xxnffc14h can main clock selection register cgcs r/w 7f05h xxnffc18h can time stamp count register cgtsc r can message search start register cgmss w xxnffc1ah can message search result register cgmsr r 0000h xxnffc40h can1 address mask 0 register l c1maskl0 xxnffc42h can1 address mask 0 register h c1maskh0 xxnffc44h can1 address mask 1 register l c1maskl1 xxnffc46h can1 address mask 1 register h c1maskh1 xxnffc48h can1 address mask 2 register l c1maskl2 xxnffc4ah can1 address mask 2 register h c1maskh2 xxnffc4ch can1 address mask 3 register l c1maskl3 xxnffc4eh can1 address mask 3 register h c1maskh3 undefined xxnffc50h can1 control register c1ctrl 0101h xxnffc52h can1 definition register c1def r/w note 2 0000h xxnffc54h can1 information register c1last 00ffh xxnffc56h can1 error count register c1erc r 0000h xxnffc58h can1 interrupt enable register c1ie r/w note 2 0900h xxnffc5ah can1 bus active register c1ba r 00ffh can1 bit rate prescaler register c1brp r/w xxnffc5ch can1 bus diagnostic information register c1dinf r 0000h xxnffc5eh can1 synchronization control register c1sync 0218h xxnffc80h can2 address mask 0 register l note 1 c2maskl0 xxnffc82h can2 address mask 0 register h note 1 c2maskh0 xxnffc84h can2 address mask 1 register l note 1 c2maskl1 xxnffc86h can2 address mask 1 register h note 1 c2maskh1 xxnffc88h can2 address mask 2 register l note 1 c2maskl2 r/w undefined notes 1 . pd703079y and 70f3079y only 2. read only remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 417 (14/14) bit units for manipulation address function register name symbol r/w 1 bit 8 bit 16 bit 32 bit after reset xxnffc8ah can2 address mask 2 register h note 1 c2maskh2 xxnffc8ch can2 address mask 3 register l note 1 c2maskl3 xxnffc8eh can2 address mask 3 register h note 1 c2maskh3 undefined xxnffc90h can2 control register note 1 c2ctrl 0101h xxnffc92h can2 definition register note 1 c2def r/w note 2 0000h xxnffc94h can2 information register note 1 c2last 00ffh xxnffc96h can2 error count register note 1 c2erc r 0000h xxnffc98h can2 interrupt enable register note 1 c2ie r/w note 2 0900h xxnffc9ah can2 bus active register note 1 c2ba r 00ffh can2 bit rate prescaler register note 1 c2brp r/w xxnffc9ch can2 bus diagnostic information register note 1 c2dinf r 0000h xxnffc9eh can2 synchronization control register note 1 c2sync r/w 0218h notes 1. pd703079y and 70f3079y only 2. read only remark n = 3, 7, b
chapter 18 fcan controller user?s manual u14665ej2v0um 418 18.4 control registers 18.4.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) the m_dlcn register sets the byte count in the data field of can message buffer n (n = 00 to 31). when receiving, the receive data field?s byte count is set (1). these registers can be read/written in 8-bit units. after reset: undefined r/w address: see table 18-3 76543210 m_dlcn 0 0 0 0 dlc3 dlc2 dlc1 dlc0 (n = 00 to 31) dlc3 dlc2 dlc1 dlc0 data length code of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of dlc3 to dlc0 values table 18-3. addresses of m_dlcn (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_dlc00 xxmff804h m_dlc16 xxmffa04h m_dlc01 xxmff824h m_dlc17 xxmffa24h m_dlc02 xxmff844h m_dlc18 xxmffa44h m_dlc03 xxmff864h m_dlc19 xxmffa64h m_dlc04 xxmff884h m_dlc20 xxmffa84h m_dlc05 xxmff8a4h m_dlc21 xxmffaa4h m_dlc06 xxmff8c4h m_dlc22 xxmffac4h m_dlc07 xxmff8e4h m_dlc23 xxmffae4h m_dlc08 xxmff904h m_dlc24 xxmffb04h m_dlc09 xxmff924h m_dlc25 xxmffb24h m_dlc10 xxmff944h m_dlc26 xxmffb44h m_dlc11 xxmff964h m_dlc27 xxmffb64h m_dlc12 xxmff984h m_dlc28 xxmffb84h m_dlc13 xxmff9a4h m_dlc29 xxmffba4h m_dlc14 xxmff9c4h m_dlc30 xxmffbc4h m_dlc15 xxmff9e4h m_dlc31 xxmffbe4h
chapter 18 fcan controller user?s manual u14665ej2v0um 419 18.4.2 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) the m_ctrln register is used to set the frame format of the data field in messages stored in can message buffer n (n = 00 to 31). these registers can be read/written in 8-bit units. (1/2) after reset: undefined r/w address: see table 18-4 76543210 m_ctrln rmde1 rmde0 ats ie movr undefined note 1 undefined note 2 rtr (n = 00 to 31) rmde1 specifies operation of dn flag when remote frame is received on a transmit message buffer 0 dn flag not set when remote frame is received 1 dn flag set when remote frame is received ? when the rmde1 bit is set, the setting of the rmde0 bit is irrelevant. ? if a remote frame is received at the transmit message buffer when the rmde1 bit has not been set, the cpu is not notified, nor are other operations performed. rmde0 specification of set/clear status of remote frame auto acknowledge function 0 remote frame auto acknowledge function cleared 1 remote frame auto acknowledge function set ? the rmde0 bit?s setting is used only for transmit messages. ? when the rtr bit has been set (1) (when the receive message or transmit message has a remote frame), the rmde0 bit is processed as rmde0 = 0. this prevents a worst-case scenario (in which transmission of a remote frame draws a 100% bus load due to reception of the same remote frame). ats specifies whether or not to add a time stamp when transmitting 0 time stamp not added when transmitting 1 time stamp added when transmitting ? the ats bit is used only for transmit messages. ? when the ats bit has been set (1) and the data length code specifies at least two bytes, the last two bytes are replaced by a time stamp (see table 18-12 ). the added time stamp counter value is sent to the bus via the message?s sof. when this occurs, the last two bytes (which are defined as a data field) are ignored. notes 1. the value of the r1 bit on the can bus is set during reception. 2. the value of the r0 bit on the can bus is set during reception. remark dn: bit 2 of m_statm (see 18.4.7 can message status registers 00 to 31 (m_stat00 to m_stat31) )
chapter 18 fcan controller user?s manual u14665ej2v0um 420 (2/2) ie specifies the enable/disable setting for interrupt requests 0 interrupt requests disabled 1 interrupt requests enabled ? an interrupt request occurs when an interrupt is enabled under the following conditions. ? when a message is sent from the transmit message buffer ? when a message is received by the receive message buffer ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has not been set (rmde0 bit = 0). ? an interrupt request does not occur when an interrupt is enabled under the following conditions. ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has been set (rmde0 bit = 1) ? when a remote frame has been transmitted from the receive message buffer movr message buffer overwrite 0 overwrite does not occur after dn bit is cleared 1 overwrite occurs at least once after dn bit is cleared ? an overwrite of the message buffer occurs when the can module writes new data to the message buffer or when the dn bit has already been set (1). the movr bit is updated each time new data is stored in the message buffer. rtr specification of frame type 0 data frame transmit/receive 1 remote frame transmit/receive ? when the rtr bit has been set (1) for a transmit message, a remote frame is transmitted instead of a data frame. remark dn: bit 2 of m_statm (see 18.4.7 can message status registers 00 to 31 (m_stat00 to m_stat31) )
chapter 18 fcan controller user?s manual u14665ej2v0um 421 table 18-4. addresses of m_ctrln (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_ctrl00 xxmff805h m_ctrl16 xxmffa05h m_ctrl01 xxmff825h m_ctrl17 xxmffa25h m_ctrl02 xxmff845h m_ctrl18 xxmffa45h m_ctrl03 xxmff865h m_ctrl19 xxmffa65h m_ctrl04 xxmff885h m_ctrl20 xxmffa85h m_ctrl05 xxmff8a5h m_ctrl21 xxmffaa5h m_ctrl06 xxmff8c5h m_ctrl22 xxmffac5h m_ctrl07 xxmff8e5h m_ctrl23 xxmffae5h m_ctrl08 xxmff905h m_ctrl24 xxmffb05h m_ctrl09 xxmff925h m_ctrl25 xxmffb25h m_ctrl10 xxmff945h m_ctrl26 xxmffb45h m_ctrl11 xxmff965h m_ctrl27 xxmffb65h m_ctrl12 xxmff985h m_ctrl28 xxmffb85h m_ctrl13 xxmff9a5h m_ctrl29 xxmffba5h m_ctrl14 xxmff9c5h m_ctrl30 xxmffbc5h m_ctrl15 xxmff9e5h m_ctrl31 xxmffbe5h 18.4.3 can message time stamp registers 00 to 31 (m_time00 to m_time31) the m_timen register is the register where the time stamp counter value is written upon completion of data reception (n = 00 to 31). these registers can be read/written in 16-bit units. when a data frame or remote frame is received in the receive message buffer, the new data is stored in the message buffer and a 16-bit time tag (time stamp counter value) is stored in the m_timen register. this time tag is set according to the fcan?s time stamp setting, which is either the time stamp counter value that was captured when the sof was sent on the can bus or the value captured when the can module writes data to the message buffer. after reset: undefined r/w address: see table 18-5 1514131211109876543210 m_timen (n = 00 to 31) ts 15 ts 14 ts 13 ts 12 ts 11 ts 10 ts 09 ts 08 ts 07 ts 06 ts 05 ts 04 ts 03 ts 02 ts 01 ts 00
chapter 18 fcan controller user?s manual u14665ej2v0um 422 table 18-5. addresses of m_timen (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_time00 xxmff806h m_time16 xxmffa06h m_time01 xxmff826h m_time17 xxmffa26h m_time02 xxmff846h m_time18 xxmffa46h m_time03 xxmff866h m_time19 xxmffa66h m_time04 xxmff886h m_time20 xxmffa86h m_time05 xxmff8a6h m_time21 xxmffaa6h m_time06 xxmff8c6h m_time22 xxmffac6h m_time07 xxmff8e6h m_time23 xxmffae6h m_time08 xxmff906h m_time24 xxmffb06h m_time09 xxmff926h m_time25 xxmffb26h m_time10 xxmff946h m_time26 xxmffb46h m_time11 xxmff966h m_time27 xxmffb66h m_time12 xxmff986h m_time28 xxmffb86h m_time13 xxmff9a6h m_time29 xxmffba6h m_time14 xxmff9c6h m_time30 xxmffbc6h m_time15 xxmff9e6h m_time31 xxmffbe6h
chapter 18 fcan controller user?s manual u14665ej2v0um 423 18.4.4 can message data registers n0 to n7 (m_datan0 to m_datan7) the m_datan0 to m_datan7 registers are areas where up to 8 bytes of transmit or receive data is stored. these registers can be read/written in 8-bit units. the m_datan0 to m_datan7 registers are fields used to hold receive data and transmit data. when data is transmitted, the number of messages defined by the dlc3 to dlc0 bits in the m_dlcn register are transmitted via the can bus. when the m_ctrln register?s ats bit has been set (1) and the value of the dlc3 to dlc0 bits in the m_dlcn register is at least two bytes, the last two bytes that are sent normally via the can bus are ignored and the time stamp value is sent. when a new message is received, all data fields are updated, even when the value of the dlc3 to dlc0 bits in the m_dlcn register is less than 8 bytes. the values of data bytes that have not been received may be updated, but they are ignored. remark n = 00 to 31, x = 0 to 7 76543210addressafter reset m_datan0 d0_7 d0_6 d0_5 d0_4 d0_3 d0_2 d0_1 d0_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan1 d1_7 d1_6 d1_5 d1_4 d1_3 d1_2 d1_1 d1_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan2 d2_7 d2_6 d2_5 d2_4 d2_3 d2_2 d2_1 d2_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan3 d3_7 d3_6 d3_5 d3_4 d3_3 d3_2 d3_1 d3_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan4 d4_7 d4_6 d4_5 d4_4 d4_3 d4_2 d4_1 d4_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan5 d5_7 d5_6 d5_5 d5_4 d5_3 d5_2 d5_1 d5_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan6 d6_7 d6_6 d6_5 d6_4 d6_3 d6_2 d6_1 d6_0 see table 18-6 undefined (n = 00 to 31) 76543210addressafter reset m_datan7 d7_7 d7_6 d7_5 d7_4 d7_3 d7_2 d7_1 d7_0 see table 18-6 undefined (n = 00 to 31)
chapter 18 fcan controller user?s manual u14665ej2v0um 424 table 18-6. addresses of m_datanx (n = 00 to 31, x = 0 to 7) register name n m_datan0 (m = 3, 7, b) m_datan1 (m = 3, 7, b) m_datan2 (m = 3, 7, b) m_datan3 (m = 3, 7, b) m_datan4 (m = 3, 7, b) m_datan5 (m = 3, 7, b) m_datan6 (m = 3, 7, b) m_datan7 (m = 3, 7, b) 00 xxmff808h xxmff809h xxmff80ah xxmff80bh xxmff80ch xxmff80dh xxmff80eh xxmff80fh 01 xxmff828h xxmff829h xxmff82ah xxmff82bh xxmff82ch xxmff82dh xxmff82eh xxmff82fh 02 xxmff848h xxmff849h xxmff84ah xxmff84bh xxmff84ch xxmff84dh xxmff84eh xxmff84fh 03 xxmff868h xxmff869h xxmff86ah xxmff86bh xxmff86ch xxmff86dh xxmff86eh xxmff86fh 04 xxmff888h xxmff889h xxmff88ah xxmff88bh xxmff88ch xxmff88dh xxmff88eh xxmff88fh 05 xxmff8a8h xxmff8a9h xxmff8aah xxmff8abh xxmff8ach xxmff8adh xxmff8aeh xxmff8afh 06 xxmff8c8h xxmff8c9h xxmff8cah xxmff8cbh xxmff8cch xxmff8cdh xxmff8ceh xxmff8cfh 07 xxmff8e8h xxmff8e9h xxmff8eah xxmff8ebh xxmff8ech xxmff8edh xxmff8eeh xxmff8efh 08 xxmff908h xxmff909h xxmff90ah xxmff90bh xxmff90ch xxmff90dh xxmff90eh xxmff90fh 09 xxmff928h xxmff929h xxmff92ah xxmff92bh xxmff92ch xxmff92dh xxmff92eh xxmff92fh 10 xxmff948h xxmff949h xxmff94ah xxmff94bh xxmff94ch xxmff94dh xxmff94eh xxmff94fh 11 xxmff968h xxmff969h xxmff96ah xxmff96bh xxmff96ch xxmff96dh xxmff96eh xxmff96fh 12 xxmff988h xxmff989h xxmff98ah xxmff98bh xxmff98ch xxmff98dh xxmff98eh xxmff98fh 13 xxmff9a8h xxmff9a9h xxmff9aah xxmff9abh xxmff9ach xxmff9adh xxmff9aeh xxmff9afh 14 xxmff9c8h xxmff9c9h xxmff9cah xxmff9cbh xxmff9cch xxmff9cdh xxmff9ceh xxmff9cfh 15 xxmff9e8h xxmff9e9h xxmff9eah xxmff9ebh xxmff9ech xxmff9edh xxmff9eeh xxmff9efh 16 xxmffa08h xxmffa09h xxmffa0ah xxmffa0bh xxmffa0ch xxmffa0dh xxmffa0eh xxmffa0fh 17 xxmffa28h xxmffa29h xxmffa2ah xxmffa2bh xxmffa2ch xxmffa2dh xxmffa2eh xxmffa2fh 18 xxmffa48h xxmffa49h xxmffa4ah xxmffa4bh xxmffa4ch xxmffa4dh xxmffa4eh xxmffa4fh 19 xxmffa68h xxmffa69h xxmffa6ah xxmffa6bh xxmffa6ch xxmffa6dh xxmffa6eh xxmffa6fh 20 xxmffa88h xxmffa89h xxmffa8ah xxmffa8bh xxmffa8ch xxmffa8dh xxmffa8eh xxmffa8fh 21 xxmffaa8h xxmffaa9h xxmffaaah xxmffaabh xxmffaach xxmffaadh xxmffaaeh xxmffaafh 22 xxmffac8h xxmffac9h xxmffacah xxmffacbh xxmffacch xxmffacdh xxmffaceh xxmffacfh 23 xxmffae8h xxmffae9h xxmffaeah xxmffaebh xxmffaech xxmffaedh xxmffaeeh xxmffaefh 24 xxmffb08h xxmffb09h xxmffb0ah xxmffb0bh xxmffb0ch xxmffb0dh xxmffb0eh xxmffb0fh 25 xxmffb28h xxmffb29h xxmffb2ah xxmffb2bh xxmffb2ch xxmffb2dh xxmffb2eh xxmffb2fh 26 xxmffb48h xxmffb49h xxmffb4ah xxmffb4bh xxmffb4ch xxmffb4dh xxmffb4eh xxmffb4fh 27 xxmffb68h xxmffb69h xxmffb6ah xxmffb6bh xxmffb6ch xxmffb6dh xxmffb6eh xxmffb6fh 28 xxmffb88h xxmffb89h xxmffb8ah xxmffb8bh xxmffb8ch xxmffb8dh xxmffb8eh xxmffb8fh 29 xxmffba8h xxmffba9h xxmffbaah xxmffbabh xxmffbach xxmffbadh xxmffbaeh xxmffbafh 30 xxmffbc8h xxmffbc9h xxmffbcah xxmffbcbh xxmffbcch xxmffbcdh xxmffbceh xxmffbcfh 31 xxmffbe8h xxmffbe9h xxmffbeah xxmffbebh xxmffbech xxmffbedh xxmffbeeh xxmffbefh
chapter 18 fcan controller user?s manual u14665ej2v0um 425 18.4.5 can message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) the m_idln and m_idhn registers are areas used to set identifiers (n = 00 to 31). these registers can be read/written in 16-bit units. when in standard format mode, any data can be stored in the following areas. id17 to id10: first byte of receive data note is stored. id9 to id2: second byte of receive data note is stored. id1, id0: third byte (higher two bits) of receive data note is stored. note see 18.4.4 can message data registers n0 to n7 (m_datan0 to m_datan7) . after reset: undefined r/w address: see table 18-7 1514131211109876543210 m_idhn (n = 00 to 31) ide 0 0 id 28 id 27 id 26 id 25 id 24 id 23 id 22 id 21 id 20 id 19 id 18 id 17 id 16 1514131211109876543210 m_idln (n = 00 to 31) id 15 id 14 id 13 id 12 id 11 id 10 id 9 id 8 id 7 id 6 id 5 id 4 id 3 id 2 id 1 id 0 ide specification of format setting mode 0 standard format mode (id28 to id18: 11 bits) 1 extended format mode (id28 to id0: 29 bits)
chapter 18 fcan controller user?s manual u14665ej2v0um 426 table 18-7. addresses of m_idln and m_idhn (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_idl00 xxmff810h m_idl16 xxmffa10h m_idh00 xxmff812h m_idh16 xxmffa12h m_idl01 xxmff830h m_idl17 xxmffa30h m_idh01 xxmff832h m_idh17 xxmffa32h m_idl02 xxmff850h m_idl18 xxmffa50h m_idh02 xxmff852h m_idh18 xxmffa52h m_idl03 xxmff870h m_idl19 xxmffa70h m_idh03 xxmff872h m_idh19 xxmffa72h m_idl04 xxmff890h m_idl20 xxmffa90h m_idh04 xxmff892h m_idh20 xxmffa92h m_idl05 xxmff8b0h m_idl21 xxmffab0h m_idh05 xxmff8b2h m_idh21 xxmffab2h m_idl06 xxmff8d0h m_idl22 xxmffad0h m_idh06 xxmff8d2h m_idh22 xxmffad2h m_idl07 xxmff8f0h m_idl23 xxmffaf0h m_idh07 xxmff8f2h m_idh23 xxmffaf2h m_idl08 xxmff910h m_idl24 xxmffb10h m_idh08 xxmff912h m_idh24 xxmffb12h m_idl09 xxmff930h m_idl25 xxmffb30h m_idh09 xxmff932h m_idh25 xxmffb32h m_idl10 xxmff950h m_idl26 xxmffb50h m_idh10 xxmff952h m_idh26 xxmffb52h m_idl11 xxmff970h m_idl27 xxmffb70h m_idh11 xxmff972h m_idh27 xxmffb72h m_idl12 xxmff990h m_idl28 xxmffb90h m_idh12 xxmff992h m_idh28 xxmffb92h m_idl13 xxmff9b0h m_idl29 xxmffbb0h m_idh13 xxmff9b2h m_idh29 xxmffbb2h m_idl14 xxmff9d0h m_idl30 xxmffbd0h m_idh14 xxmff9d2h m_idh30 xxmffbd2h m_idl15 xxmff9f0h m_idl31 xxmffbf0h m_idh15 xxmff9f2h m_idh31 xxmffbf2h
chapter 18 fcan controller user?s manual u14665ej2v0um 427 18.4.6 can message configuration registers 00 to 31 (m_conf00 to m_conf31) the m_confn register is used to specify the message buffer type and mask setting (n = 00 to 31). these registers can be read/written in 8-bit units. after reset: undefined r/w address: see table 18-8 76543210 m_confn 0 0 mt2 mt1 mt0 ma2 ma1 ma0 (n = 00 to 31) mt2 mt1 mt0 specification of message type and mask setting 0 0 0 transmit message 0 0 1 receive message (no mask setting) 0 1 0 receive message (mask 0 is set) 0 1 1 receive message (mask 1 is set) 1 0 0 receive message (mask 2 is set) 1 0 1 receive message (mask 3 is set) 1 1 0 setting prohibited 1 1 1 receive message (used in diagnostic processing mode) ? when bits mt2 to mt0 have been set as ?111?, processing can be performed only when the fcan has been set to diagnostic processing mode. in such cases, all messages received are stored regardless of the following conditions. ? storage to other message buffer ? identifier type (standard frame or extended frame) ? data frame or remote frame ma2 ma1 ma0 message buffer?s address specification 0 0 0 message buffer is not used 0 0 1 used as message buffer of can module 1 010 used as message buffer of can module 2 note other than above setting prohibited ? when bits ma2, ma1, and ma0 have been set to ?000?, message buffer area is used for application ram or for event processing as a temporary buffer. note pd703079y and 70f3079y only
chapter 18 fcan controller user?s manual u14665ej2v0um 428 table 18-8. addresses of m_confn (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_conf00 xxmff814h m_conf16 xxmffa14h m_conf01 xxmff834h m_conf17 xxmffa34h m_conf02 xxmff854h m_conf18 xxmffa54h m_conf03 xxmff874h m_conf19 xxmffa74h m_conf04 xxmff894h m_conf20 xxmffa94h m_conf05 xxmff8b4h m_conf21 xxmffab4h m_conf06 xxmff8d4h m_conf22 xxmffad4h m_conf07 xxmff8f4h m_conf23 xxmffaf4h m_conf08 xxmff914h m_conf24 xxmffb14h m_conf09 xxmff934h m_conf25 xxmffb34h m_conf10 xxmff954h m_conf26 xxmffb54h m_conf11 xxmff974h m_conf27 xxmffb74h m_conf12 xxmff994h m_conf28 xxmffb94h m_conf13 xxmff9b4h m_conf29 xxmffbb4h m_conf14 xxmff9d4h m_conf30 xxmffbd4h m_conf15 xxmff9f4h m_conf31 xxmffbf4h
chapter 18 fcan controller user?s manual u14665ej2v0um 429 18.4.7 can message status registers 00 to 31 (m_stat00 to m_stat31) the m_statn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). these registers are read-only, in 8-bit units. cautions 1. writing directly to m_statn register cannot be performed. writing must be performed using can status set/clear register n (sc_statn). 2. messages are transmitted only when the m_statn register?s trq and rdy bits have been set (1). after reset: undefined r address: see table 18-9 76543210 m_statn 0 0 0 0 0 dn trq rdy note (n = 00 to 31) dn message update flag 0 no message was received after dn bit was cleared 1 at least one message was received after dn bit was cleared ? when the dn bit has been set (1) by the transmit message buffer, it indicates that the message buffer has received a remote frame. when this message is sent, the dn bit is automatically cleared (0). ? when a frame is again received in the message buffer for which the dn bit has been set (1), an overwrite condition occurs and the m_ctrln register?s movr bit is set (1). trq transmit request flag 0 message transmission prohibited 1 message transmission enabled rdy transmit message ready flag 0 transmit message is not ready 1 transmit message is ready ? a receive operation is performed only for a message buffer in which the rdy bit is set to 1 during reception. ? a transmit operation is performed only for a message buffer in which the rdy bit is set to 1 and the trq bit is set to 1 during transmission. note the fcan controller incorporated in the v850/sf1 can perform reception even if the rdy bit is not set. however, in products other than the v850/sf1, the rdy bit must be set for reception. in order to maintain software compatibility, be sure to set the rdy bit even for the fcan controller of the v850/sf1 prior to reception.
chapter 18 fcan controller user?s manual u14665ej2v0um 430 table 18-9. addresses of m_statn (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) m_stat00 xxmff815h m_stat16 xxmffa15h m_stat01 xxmff835h m_stat17 xxmffa35h m_stat02 xxmff855h m_stat18 xxmffa55h m_stat03 xxmff875h m_stat19 xxmffa75h m_stat04 xxmff895h m_stat20 xxmffa95h m_stat05 xxmff8b5h m_stat21 xxmffab5h m_stat06 xxmff8d5h m_stat22 xxmffad5h m_stat07 xxmff8f5h m_stat23 xxmffaf5h m_stat08 xxmff915h m_stat24 xxmffb15h m_stat09 xxmff935h m_stat25 xxmffb35h m_stat10 xxmff955h m_stat26 xxmffb55h m_stat11 xxmff975h m_stat27 xxmffb75h m_stat12 xxmff995h m_stat28 xxmffb95h m_stat13 xxmff9b5h m_stat29 xxmffbb5h m_stat14 xxmff9d5h m_stat30 xxmffbd5h m_stat15 xxmff9f5h m_stat31 xxmffbf5h
chapter 18 fcan controller user?s manual u14665ej2v0um 431 18.4.8 can status set/clear registers 00 to 31 (sc_stat00 to sc_stat31) the sc_statn register is used to set/clear the transmit/receive status information (n = 00 to 31). these registers are write-only, in 16-bit units. after reset: 0000h w address: see table 18-10 15 14 13 12 11 10 9 8 sc_statn 0 0 0 0 0 set dn set trq set rdy (n = 00 to 31) 76543210 0 0 0 0 0 clear dn clear trq clear rdy set dn clear dn message update flag setting 0 1 clear (clear dn bit) 1 0 set (set dn bit) other than above no change in dn bit value set trq clear trq transmit request flag setting 0 1 clear (clear trq bit) 1 0 set (set trq bit) other than above no change in trq bit value set rdy clear rdy message ready flag setting 0 1 clear (clear rdy bit) 1 0 set (set rdy bit) other than above no change in rdy bit value remark dn: bit 2 of can message status register n (m_statn) trq: bit 1 of can message status register n (m_statn) rdy: bit 0 of can message status register n (m_statn)
chapter 18 fcan controller user?s manual u14665ej2v0um 432 table 18-10. addresses of sc_statn (n = 00 to 31) register name address (m = 3, 7, b) register name address (m = 3, 7, b) sc_stat00 xxmff816h sc_stat16 xxmffa16h sc_stat01 xxmff836h sc_stat17 xxmffa36h sc_stat02 xxmff856h sc_stat18 xxmffa56h sc_stat03 xxmff876h sc_stat19 xxmffa76h sc_stat04 xxmff896h sc_stat20 xxmffa96h sc_stat05 xxmff8b6h sc_stat21 xxmffab6h sc_stat06 xxmff8d6h sc_stat22 xxmffad6h sc_stat07 xxmff8f6h sc_stat23 xxmffaf6h sc_stat08 xxmff916h sc_stat24 xxmffb16h sc_stat09 xxmff936h sc_stat25 xxmffb36h sc_stat10 xxmff956h sc_stat26 xxmffb56h sc_stat11 xxmff976h sc_stat27 xxmffb76h sc_stat12 xxmff996h sc_stat28 xxmffb96h sc_stat13 xxmff9b6h sc_stat29 xxmffbb6h sc_stat14 xxmff9d6h sc_stat30 xxmffbd6h sc_stat15 xxmff9f6h sc_stat31 xxmffbf6h
chapter 18 fcan controller user?s manual u14665ej2v0um 433 18.4.9 can interrupt pending register (ccintp) the ccintp register is used to confirm the pending status of various interrupts. this register is read-only in 16-bit units. after reset: 0000h r address: xxmffc00h (m = 3, 7, b) 15 14 13 12 11 10 9 8 ccintp 0 intmac 0 0 0 0 0 0 76543210 0 0 can2err can2rec can2trx can1err can1rec can1trx intmac pending status of mac error note 1 interrupts (gint3 to gint1) 0 not pending 1 pending can2err note 2 pending status of can2 access error interrupt (c2int6 to c2int2) 0 not pending 1 pending can2rec note 2 pending status of can2 receive completion interrupt (c2int1) 0 not pending 1 pending can2trx note 2 pending status of can2 transmit completion interrupt (c2int0) 0 not pending 1 pending can1err pending status of can1 access error interrupt (c1int6 to c1int2) 0 not pending 1 pending can1rec pending status of can1 receive completion interrupt (c1int1) 0 not pending 1 pending can1trx pending status of can1 transmit completion interrupt (c1int0) 0 not pending 1 pending notes 1. mac (message access control) errors are errors that are set only when an interrupt source has occurred for the can global interrupt pending register (cgintp). 2. pd703079y and 70f3079y only remark gint3 to gint1: bits 3 to 1 of the can global interrupt pending register (cgintp) cnint6 to cnint0 (n = 1, 2): bits 6 to 0 of the cann interrupt pending register (cnintp)
chapter 18 fcan controller user?s manual u14665ej2v0um 434 18.4.10 can global interrupt pending register (cgintp) the cgintp register is used to confirm the pending status of mac access error interrupts. this register can be read/written in 8-bit units. cautions 1. when ?1? is written to a bit in the cgintp register, that bit is cleared (0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. the correct or incorrect timing of setting the interrupt pending bit (1) is controlled by an interrupt service routine. the earlier that the interrupt service routine clears the interrupt pending bit (0), the more quickly the interrupt occurs without losing any new interrupts of the same type. the interrupt pending bit can be set (1) only when the interrupt enable bit has been set (1). however, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). use software processing to clear the interrupt pending bit (0). remark for details of invalid write access error interrupts and unavailable memory address access error interrupts, see 18.15.2 interrupts that occur for global can interface . after reset: 00h r/w address: xxmffc02h (m = 3, 7, b) 76543210 cgintp0000gint3gint2gint10 gint3 pending status of wake-up interrupt (from can sleep mode with stopped clock supply to fcan) 0 not pending 1 pending gint2 pending status of invalid write access error interrupt 0 not pending 1 pending gint1 pending status of unavailable memory address access error interrupt 0 not pending 1 pending
chapter 18 fcan controller user?s manual u14665ej2v0um 435 18.4.11 cann interrupt pending register (cnintp) the cnintp register is used to confirm the pending status of interrupts issued to the can. this register can be read/written in 8-bit units. the can2 interrupt pending register (c2intp) is valid only in models pd703079y and 70f3079y. cautions 1. when ?1? is written to a bit in the cnintp register, that bit is cleared (0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. the correct or incorrect timing of setting the interrupt pending bit (1) is controlled by an interrupt service routine. the earlier that the interrupt service routine clears the interrupt pending bit (0), the more quickly the interrupt occurs without losing any new interrupts of the same type. the interrupt pending bit can be set (1) only when the interrupt ready bit has been set (1). however, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). use software processing to clear the interrupt pending bit (0). remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 436 after reset: 00h r/w addresses: c1intp: xxmffc04h (m = 3, 7, b) c2intp: xxmffc06h (m = 3, 7, b) 76543210 cnintp 0 cnint6 cnint5 cnint4 cnint3 cnint2 cnint1 cnint0 (n = 1, 2) cnint6 pending status of can error interrupt 0 not pending 1 pending cnint5 pending status of can bus error interrupt 0 not pending 1 pending cnint4 pending status of wake-up interrupt (from can sleep mode) 0 not pending 1 pending cnint3 pending status of can receive error passive status interrupt 0 not pending 1 pending cnint2 pending status of can transmit error passive or bus off status interrupt 0 not pending 1 pending cnint1 pending status of can receive completion interrupt 0 not pending 1 pending cnint0 pending status of can transmit completion interrupt 0 not pending 1 pending
chapter 18 fcan controller user?s manual u14665ej2v0um 437 18.4.12 can stop register (cstop) the cstop register controls clock supply to the entire can system. this register can be read/written in 16-bit units. cautions 1. be sure to set the cstp bit (1) if the fcan function will not be used. 2. when the cstp bit is set (1), access to fcan registers other than the cstop register is prohibited. access to fcan (other than the cstop register) is possible only when the cstp bit is not set (1). 3. when a change occurs on the can bus via a cstp setting while the clock supply to the cpu or peripheral functions is stopped, the cpu can be woken up. after reset: 0000h r/w address: xxmffc0ch (m = 3, 7, b) 1514131211109876543210 cstop cstp 000000000000000 cstp controls clock supply to fcan 0 fcan in operation (supplies clock to fcan blo cks) 1 fcan is stopped (access to fcan blo cks is not possible)
chapter 18 fcan controller user?s manual u14665ej2v0um 438 18.4.13 can global status register (cgst) the cgst register indicates global status information. this register can be read in 16- or 8-bit units and written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgst register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 cautions regarding bit set/clear function. 2. when writing to the cgst register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/2) after reset: 0100h r/w address: xxmffc10h (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cgst00000001 76543210 merr 0 0 0 efsd tsm 0 gom (b) write151413121110 9 8 cgst 0 0 0 0 set efsd set tsm 0 set gom 76543210 clear merr 000 clear efsd clear tsm 0 clear gom (a) read merr mac error status flag 0 error does not occur after the merr bit has been cleared 1 error occurs at least once after merr bit has been cleared ? mac errors occur when an access to an invalid ram address is attempted. efsd shutdown request 0 shutdown prohibited 1 shutdown enabled ? be sure to set the efsd bit (1) before clearing the gom bit (0) (must be accessed twice). the efsd bit will be cleared (0) automatically when the cgst register is accessed again. tsm operation status of time stamp counter note 0 time stamp counter is stopped 1 time stamp counter is operating note see 18.4.16 can time stamp count register (cgtsc).
chapter 18 fcan controller user?s manual u14665ej2v0um 439 (2/2) (a) read gom status of global operation mode 0 access to can module register note is prohibited 1 access to can module register note is enabled ? the gom bit controls the method the memory is accessed by the mac. ? when gom bit = 0 ? access to can module register disabled (if accessed, mac error interrupt occurs) ? read/write access to temporary buffer enabled ? access to message buffer area enabled ? when gom bit = 1 ? access to can module register enabled ? only read access to temporary buffer enabled (if write access is attempted, mac error interrupt occurs) ? access to message buffer area enabled ? the gom bit is cleared (0) only when all the can modules are in the initial status (the istat bit of the cnctr register is 1). even if the gom bit is cleared when there is a can module not in the initial status, the gom bit remains set (1). (b) write set efsd clear efsd efsd bit enable 0 1 efsd bit cleared 1 0 efsd bit set other than above no change in value of efsd bit set tsm clear tsm tsm bit enable 0 1 tsm bit cleared 10tsm bit set other than above no change in value of tsm bit set gom clear gom gom bit enable 0 1 gom bit cleared 1 0 gom bit set other than above no change in value of gom bit clear merr merr bit enable 0 no change in value of merr bit 1 merr bit cleared note register with a name starting with ?cn? (n = 1, 2)
chapter 18 fcan controller user?s manual u14665ej2v0um 440 18.4.14 can global interrupt enable register (cgie) the cgie register is used to issue interrupt requests for global interrupts. this register can be read in 16- or 8-bit units and written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 cautions regarding bit set/clear function. 2. when writing to the cgie register, set or clear bits according to the register configuration shown in part (b) write of the following figure. after reset: 0a00h r/w address: xxmffc12h (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cgie00001010 76543210 00000g_ie2g_ie10 (b) write151413121110 9 8 cgie 0 0 0 0 0 set g_ie2 set g_ie1 0 76543210 0000 0 clear g_ie2 clear g_ie1 0 (a) read g_ie2 interrupt enable status for invalid write access (to temporary buffer, etc.) 0 interrupt disabled 1 interrupt enabled g_ie1 interrupt enable status for memory access to reserved address 0 interrupt disabled 1 interrupt enabled (b) write set g_ien clear g_ien setting of g_ien bit 0 1 clear g_ien bit 1 0 set g_ien bit other than above no change remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 441 18.4.15 can main clock select register (cgcs) the cgcs register is used to select the main clock. this register can be read/written in 16-bit units. after reset: 7f05h r/w address: xxmffc14h (m = 3, 7, b) 15 14 13 12 11 10 9 8 cgcs cgts7 cgts6 cgts5 cgts4 cgts3 cgts2 cgts1 cgts0 76543210 gtcs1 gtcs0 0 0 mcp3 mcp2 mcp1 mcp0 n cgts 7 cgts 6 cgts 5 cgts 4 cgts 3 cgts 2 cgts 1 cgts 0 system timer prescaler selection f gts = f gts1 / (n + 1) 000000000f gts = f gts1 /1 100000001f gts = f gts1 /2 :f gts = f gts1 /(n + 1) 12701111111f gts = f gts1 /128 (after reset) :f gts = f gts1 /(n + 1) 25411111110f gts = f gts1 /255 25511111111f gts = f gts1 /256 the global time system clock (f gts ) is the source clock for the time stamp counter note that is used for the time stamp function. gtcs1 gtcs0 global timer clock selection (f gts1 ) 00f mem /2 01f mem /4 10f mem /8 11f mem /16 n mcp3 mcp2 mcp1 mcp0 selection of clock to memory access controller (f mem ) 00000f mem1 10001f mem1 /2 20010f mem1 /3 : 141110f mem1 /15 151111f mem1 /16 note see 18.4.16 can time stamp count register (cgtsc) .
chapter 18 fcan controller user?s manual u14665ej2v0um 442 figure 18-2. fcan clocks note when the tlm bit of the cann bit rate prescaler register (cnbrp) is 1. caution when using a 1 mbps transfer rate for the cpu, input f mem1 as a 16 mhz clock signal. if input at another frequency, subsequent operation is not guaranteed. remark f mem1 = f xx = main clock frequency cgts7 cgts6 cgts5 cgts4 cgts3 cgts2 cgts1 cgts0 gtcs1 gtcs0 mcp 3 mcp2 prescaler data bit time cann bit rate prescaler register (cnbrp) fcan main clock select register (cgcs) global timer clock prescaler baud rate generator global timer system clock cann synchronization control register (cnsync) time stamp counter mcp1 mcp0 brp0 brp1 brp2 brp3 brp4 brp5 btype f mem1 f mem f gts1 f btl f gts brp6 note brp7 note
chapter 18 fcan controller user?s manual u14665ej2v0um 443 18.4.16 can time stamp count register (cgtsc) the cgtsc register indicates the contents of the time stamp counter. this register can be read at any time. this register can be written to only when clearing bits. the clear function writes 0 to all bits in the cgtsc register. this register is read-only, in 16-bit units. after reset: 0000h r address: xxmffc18h (m = 3, 7, b) 15 14 13 12 11 10 9 8 cgtsc tsc15 tsc14 tsc13 tsc12 tsc11 tsc10 tsc9 tsc8 76543210 tsc7 tsc6 tsc5 tsc4 tsc3 tsc2 tsc1 tsc0
chapter 18 fcan controller user?s manual u14665ej2v0um 444 18.4.17 can message search start/result register (cgmss/cgmsr) the cgmss/cgmsr register indicates the message search start/result status. messages in the message buffer that match the specified search criteria can be searched quickly. these registers can be read/written in 16-bit units. (1/2) after reset: 0000h r/w address: xxmffc1ah (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cgmsr000000mmam 76543210 0 0 0 mfnd4 mfnd3 mfnd2 mfnd1 mfnd0 (b) write151413121110 9 8 cgmss cide 0 ctrq cmsk cdn 0 smno1 smno0 76543210 0 0 0 strt4 strt3 strt2 strt1 strt0 (a) read mm confirmation of multiple hits from message search 0 no messages or only one message meets the search criteria 1 several messages meet the search criteria if several message buffers that meet the search criteria are detected, the mm bit is set. am confirmation of hits from message search 0 no messages meet the search criteria 1 at least one message meets the search criteria mfnd4 to mfnd0 searched message number this indicates the number (0 to 31) of the searched message. ? when multiple message buffer numbers match as a result of a search (mm = 1), the return value of bits mfnd4 to mfnd0 is the lowest message buffer number. when no message buffer numbers match (am = 0), the return value of bits mfnd4 to mfnd0 is ?message buffer number ? 1?.
chapter 18 fcan controller user?s manual u14665ej2v0um 445 (2/2) (b) write cide message identifier (id) format flag check 0 message identifier format flag not checked 1 message with standard format identifier checked ctrq transmit request and message ready flag check 0 transmit request and message ready flags not checked 1 transmit request and message ready flags checked cmsk masked message check 0 masked messages not checked 1 only masked messages checked cdn status check of m_statn register?s dn flag (n = 00 to 31) 0 status of m_statn register ? s dn flag not checked 1 status of m_statn register ? s dn flag checked smno1 smno0 search module setting 0 0 no search module setting 0 1 can module 1 is set as the searched target 1 0 can module 2 is set as the searched target 1 1 setting prohibited strtn message search start position (n = 0 to 4) 0 to 31 message search start position (message number) ? search starts from the message number defined by bits strt4 to strt0. search continues until it reaches the message buffer having the highest number among the usable message buffers. if the search results include several message buffer numbers among the matching messages, the message buffer with the lowest message buffer number is selected. to fetch the next message buffer number without changing the search criteria, ?(mfnd4 to mfnd0) + 1? must be set as the values of bits strt4 to strt0.
chapter 18 fcan controller user?s manual u14665ej2v0um 446 18.4.18 cann address mask a registers l and h (cnmaskla and cnmaskha) the cnmaskla and cnmaskha registers are used to extend the number of receivable messages by masking part of the message?s identifier (id) and then ignoring the masked parts. these registers can be read/written in 16-bit units. the c2maskla and c2maskha registers are valid only in models pd703079y and 70f3079y. cautions 1. when the receive message buffer is linked to the cnmaskla and cnmaskha registers, regardless of whether the id in the receive message buffer is a standard id (11 bits) or an extended id (29 bits), set all the 32-bit values of the cnmaskla and cnmaskha registers (a = 0 to 3, n = 1, 2). 2. when the cnmaskla and cnmaskha registers are linked to the message buffer for standard ids, the lower 18 bits of the data field in the data frame are also automatically compared. therefore, if it is not necessary to compare the lower 18 bits (masking), set (1) the cmid17 to cmid0 bits (a = 0 to 3, n = 1, 2). after reset: undefined r/w address: see table 18-11 15 14 13 12 11 10 9 8 cnmaskha cmide 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (a = 0 to 3, n = 1, 2) 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 15 14 13 12 11 10 9 8 cnmaskla cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 (a = 0 to 3, n = 1, 2) 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cmide mask setting for identifier (id) format 0 id format (standard or extended) checked 1 id format (standard or extended) not checked cmid0 to cmid28 mask setting for identifier (id) bits 0 id bit in message buffer linked to bits cmid28 to cmid0 compared with received id bit. 1 id bit in message buffer linked to bits cmid28 to cmid0 not compared with received id bit (i.e., masked).
chapter 18 fcan controller user?s manual u14665ej2v0um 447 table 18-11. addresses of cnmaskla and cnmaskha (a = 0 to 3, n = 1, 2) register name address (m = 3, 7, b) register name address (m = 3, 7, b) c1maskl0 xxmffc40h c2maskl0 xxmffc80h c1maskh0 xxmffc42h c2maskh0 xxmffc82h c1maskl1 xxmffc44h c2maskl1 xxmffc84h c1maskh1 xxmffc46h c2maskh1 xxmffc86h c1maskl2 xxmffc48h c2maskl2 xxmffc88h c1maskh2 xxmffc4ah c2maskh2 xxmffc8ah c1maskl3 xxmffc4ch c2maskl3 xxmffc8ch c1maskh3 xxmffc4eh c2maskh3 xxmffc8eh
chapter 18 fcan controller user?s manual u14665ej2v0um 448 18.4.19 cann control register (cnctrl) the cnctrl register is used to control the operation of the can module. this register can be read/written in 16-bit units. the c2ctrl register is valid only in models pd703079y and 70f3079y. cautions 1. both bitwise writing and direct writing to the cnctrl register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 cautions regarding bit set/clear function. 2. when writing to the cnctrl register, set or clear bits according to the register configuration shown in part (b) write of the following figure. 3. when canceling can stop mode, can sleep mode must be canceled at the same time. (1/4) after reset: 0101h r/w addresses: c1ctrl: xxmffc50h (m = 3, 7, b) c2ctrl: xxmffc90h (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cnctrl tecs1 tecs0 recs1 recs0 boff tstat rstat istat (n = 1, 2)76543210 0 dlevr dlevt ovm tmr stop sleep init (b) write151413121110 9 8 cnctrl 0 set dlevr set dlevt set ovm set tmr set stop set sleep set init (n = 1, 2)76543210 0 clear dlevr clear dlevt clear ovm clear tmr clear stop clear sleep clear init (a) read tecs1 tecs0 status of transmit error counter 0 0 transmit error counter value < 96 0 1 transmit error counter value = 96 to 127 (warning level) 1 0 not used 1 1 transmit error counter value 128 (error passive) recs1 recs0 status of receive error counter 0 0 receive error counter value < 96 0 1 receive error counter value = 96 to 127 (warning level) 1 0 not used 1 1 receive error counter value 128 (error passive) boff bus off flag 0 transmit error counter value < 256 (not bus off status) 1 transmit error counter value 256 (bus off status)
chapter 18 fcan controller user?s manual u14665ej2v0um 449 (2/4) (a) read tstat transmit status flag 0 transmit stop status 1 transmit operating status rstat receive status flag 0 receive stop status 1 receive operating status istat initialization status flag 0 normal operating status 1 fcan is stopped and initialized ? the istat bit is set (1) when the can protocol layer acknowledges the setting of the init bit and stop bit. the istat bit is automatically cleared (0) after the init bit and stop bit are cleared (0). ? when the istat bit has been set (1): ?receive? is output via the cantxn pin during initialization mode. ? the cnsync and cnbrp registers can be written only during initialization mode. ? in the initialization status, the error counter (see 18.4.22 cann error count register (cnerc) ) is cleared (0) and the error status (bit tecs1, tecs0, recs1, and recs0) is reset. dlevr dominant level control bit for receive pin 0 a low level to a receive pin is acknowledged as dominant 1 a high level to a receive pin is acknowledged as dominant dlevt dominant level control bit for transmit pin 0 a low level is transmitted from transmit pin as dominant 1 a high level is transmitted from transmit pin as dominant ovm overwrite mode control bit 0 new messages stored in message buffer in which dn bit of m_stata register is set (a = 00 to 31) 1 new messages in message buffer in which dn bit is set (a = 00 to 31) discarded tmr time stamp control bit for reception 0 when the sof is detected on the can bus, the value of the time stamp counter is captured. 1 when the eof is detected on the can bus (a valid message is confirmed), the value of the time stamp counter is captured.
chapter 18 fcan controller user?s manual u14665ej2v0um 450 (3/4) (a) read stop can stop mode control bit 0 no can stop mode setting 1 can stop mode ? can stop mode can be selected only when the can module has been set to can sleep mode, i.e., when the sleep bit has been set (1). can stop mode can be canceled only by the cpu by clearing the stop bit (0). sleep can sleep mode control bit 0 normal operating mode 1 switch to can sleep mode (change in can bus performs wake-up) ? can sleep mode is canceled under the following conditions. ? when the cpu has cleared the sleep bit (0) ? when the can bus changes (this occurs only when can stop mode has not been set) ? the wake bit note is set (1) only when can sleep mode is canceled by the change of the can bus. init initialization request bit 0 normal operating mode 1 initialization mode ? be sure to confirm that the can module has entered the initialization mode using the istat bit (istat bit = 1) after setting the init bit (1). when the istat bit = 0, set the init bit again. ? if the init bit is set (1) when the can module is in the bus off status (boff bit = 1), the can module enters initialization mode (istat bit = 1) after returning from the bus off status (boff bit = 0). note see 18.4.20 cann definition register (cndef).
chapter 18 fcan controller user?s manual u14665ej2v0um 451 (4/4) (b) write set dlevr clear dlevr dlevr bit setting 0 1 dlevr bit cleared 1 0 dlevr bit set other than above dlevr bit not changed set dlevt clear dlevt dlevt bit setting 0 1 dlevt bit cleared 10dlevt bit set other than above dlevt bit not changed set ovm clear ovm ovm bit setting 0 1 ovm bit cleared 10ovm bit set other than above ovm bit not changed set tmr clear tmr tmr bit setting 0 1 tmr bit cleared 10tmr bit set other than above tmr bit not changed set stop clear stop stop bit setting 0 1 stop bit cleared 1 0 stop bit set other than above stop bit not changed set sleep clear sleep sleep bit setting 0 1 sleep bit cleared 1 0 sleep bit set other than above sleep bit not changed set init clear init init bit setting 0 1 init bit cleared 1 0 init bit set other than above init bit not changed
chapter 18 fcan controller user?s manual u14665ej2v0um 452 18.4.20 cann definition register (cndef) the cndef register is used to define the operation of the can module. this register can be read in 16- or 8-bit units and written in 16-bit units. the c2def register is valid only in models pd703079y and 70f3079y. cautions 1. both bitwise writing and direct writing to the cndef register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 cautions regarding bit set/clear function. 2. when writing to the cndef register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/3) after reset: 0000h r/w addresses: c1def: xxmffc52h (m = 3, 7, b) c2def: xxmffc92h (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cndef00000000 (n = 1, 2)76543210 dgm mom ssht pbb berr valid wake ovr (b) write151413121110 9 8 cndef set dgm set mom set ssht set pbb 0 0 0 0 (n = 1, 2)76543210 clear dgm clear mom clear ssht clear pbb clear berr clear valid clear wake clear ovr (a) read dgm specification of diagnostic processing mode 0 valid messages received using message buffer used for diagnostic processing mode note (only when receiving) 1 valid messages received using normal operating mode (only when receiving) ? the diagnostic processing mode (mom bit = 1) is used for can baud rate detection and for diagnostic purposes. when this mode has been set, the following operations are performed. ? when the valid bit = 1, it indicates that the current receive operation is valid. ? setting the dgm bit confirms whether or not valid data has been stored in the message buffer used for diagnostic processing mode, the same as for normal operating mode. ? the can protocol layer does not sent ack, error frame, or transmit messages, nor does it operate an error counter. note bits 5 to 3 (mt2 to mt0) of can message configuration register a (m_confa) are set as ?111? (a = 00 to 31).
chapter 18 fcan controller user?s manual u14665ej2v0um 453 (2/3) (a) read mom specification of can module?s operating mode 0 normal operating mode 1 diagnostic processing mode ? when in diagnostic processing mode (mom bit = 1), the cnbrp register can be accessed only when the can module has been set to initialization mode (i.e., when the cnctrl register?s istat bit = init bit = 1). when the can module is operating (i.e., when the cnctrl register?s istat bit = 0) the cnbrp register cannot be used, and the cann bus diagnostic information register (cndinf) register can be used instead. ssht specification of single shot mode 0 normal operating mode 1 single shot mode ? during single shot mode, the can module can transmit a message only one time. the m_stata (a = 00 to 31) register?s trq bit is then cleared (0) regardless of whether or not there are any pending normal transmit operations. also, if a bus error has occurred due to a transmission, it is handled as an incomplete transmission. ? during single shot mode, even if the can lost in arbitration, it is handled as a completed message transmission. when in this mode, the berr bit is set (1) but the error counter value does not change since there are no can bus errors. ? during the time when the can module is active, the cpu switches between normal operating mode and single shot mode without causing any errors to occur on the can bus. pbb specification of priority control for transmission 0 identifier (id) based priority control 1 message number based priority control ? ordinarily, priority for transmission is defined based on message ids, but when the pbb bit has been set (1) priority becomes based instead on the position of messages, so that messages with lower message numbers have higher priority. berr can bus error status 0 can bus error was not detected 1 can bus error was detected at least once after bit was cleared valid valid message detection status 0 valid message was not detected 1 valid message was detected at least once after bit was cleared wake can sleep mode cancellation status 0 normal operation 1 cancel can sleep mode
chapter 18 fcan controller user?s manual u14665ej2v0um 454 (3/3) (a) read ovr overrun error status 0 normal operation 1 overwrite occurred during ram access ? when an overrun error has occurred, the ovr bit is set (1) and an error interrupt occurs at the same time. the source of the overrun error may be that the ram access clock is slower than the selected can baud rate. (b) write set dgm clear dgm dgm bit setting 0 1 dgm bit cleared 10dgm bit set other than above dgm bit not changed set mom clear mom mom bit setting 0 1 mom bit cleared 1 0 mom bit set other than above mom bit not changed set ssht clear ssht ssht bit setting 0 1 ssht bit cleared 10ssht bit set other than above ssht bit not changed set pbb clear pbb pbb bit setting 0 1 pbb bit cleared 1 0 pbb bit set other than above pbb bit not changed clear berr berr bit setting 1 berr bit cleared 0 berr bit not changed clear valid valid bit setting 1 valid bit cleared 0 valid bit not changed clear wake wake bit setting 1 wake bit cleared 0 wake bit not changed clear ovr ovr bit setting 1 ovr bit cleared 0 ovr bit not changed
chapter 18 fcan controller user?s manual u14665ej2v0um 455 18.4.21 cann information register (cnlast) the cnlast register indicates the cann module?s error information and the number of the message buffer received last. this register is read-only, in 16-bit units. the c2last register is valid only in models pd703079y and 70f3079y. after reset: 00ffh r addresses: c1last: xxmffc54h (m = 3, 7, b) c2last: xxmffc94h (m = 3, 7, b) 15 14 13 12 11 10 9 8 cnlast 0 0 0 0 lerr3 lerr2 lerr1 lerr0 (n = 1, 2)76543210 lrec7 lrec6 lrec5 lrec4 lrec3 lrec2 lrec1 lrec0 lerr3 lerr2 lerr1 lerr0 last error information 0 0 0 0 error not detected 0001bit error 0010stuff error 0011crc error 0 1 0 0 form error 0101ack error 0 1 1 0 arbitration lost (only during single shot mode) (cndef: ssht = 1) 0 1 1 1 can overrun error 1 0 0 0 wake-up from can bus other than above setting prohibited ? since bits lerr3 to lerr0 cannot be cleared, the current status is retained until the next error occurs. lrec7 to lrec0 number of last receive message 0 to 31 message number of message last received 32 to 255 not used
chapter 18 fcan controller user?s manual u14665ej2v0um 456 18.4.22 cann error count register (cnerc) the cnerc register indicates the count values of the transmission/reception error counters. this register is read-only in 16-bit units. the c2erc register is valid only in models pd703079y and 70f3079y. after reset: 0000h r addresses: c1erc: xxmffc56h (m = 3, 7, b) c2erc: xxmffc96h (m = 3, 7, b) 15 14 13 12 11 10 9 8 cnerc rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 (n = 1, 2)76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 rec7 to rec0 reception error counter 0 to 255 number of reception error counts ? this reflects the current status of the reception error counter. ? the count value is defined by the can protocol. tec7 to tec0 transmission error counter 0 to 255 number of transmission error counts ? this reflects the current status of the transmission error counter. ? the number of counts is defined by the can protocol.
chapter 18 fcan controller user?s manual u14665ej2v0um 457 18.4.23 cann interrupt enable register (cnie) the cnie register is used to enable/disable the can module?s interrupts. this register can be read in 16- or 8-bit units and written in 16-bit units. the c2ie register is valid only in models pd703079y and 70f3079y. cautions 1. both bitwise writing and direct writing to the cnie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 cautions regarding bit set/clear function. 2. when writing to the cnie register, set or clear bits according to the register configuration shown in part (b) write of the following figure. (1/2) after reset: 0900h r/w addresses: c1ie: xxmffc58h (m = 3, 7, b) c2ie: xxmffc98h (m = 3, 7, b) (a) read 15 14 13 12 11 10 9 8 cnie00001001 (n = 1, 2)76543210 0 e_int6 e_int5 e_int4 e_int3 e_int2 e_int1 e_int0 (b) write151413121110 9 8 cnie 0 set e_int6 set e_int5 set e_int4 set e_int3 set e_int2 set e_int1 set e_int0 (n = 1, 2)76543210 0 clear e_int6 clear e_int5 clear e_int4 clear e_int3 clear e_int2 clear e_int1 clear e_int0 (a) read e_int6 can module error interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int5 can bus error interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int4 wake up from can sleep mode interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int3 receive error passive interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int2 receive error passive or bus off interrupt enable flag 0 interrupt disabled 1 interrupt enabled
chapter 18 fcan controller user?s manual u14665ej2v0um 458 (2/2) (a) read e_int1 receive completion interrupt enable flag 0 interrupt disabled 1 interrupt enabled e_int0 transmit completion interrupt enable flag 0 interrupt disabled 1 interrupt enabled (b) write set e_int6 clear e_int6 e_int6 bit setting 0 1 e_int6 interrupt cleared 1 0 e_int6 interrupt set other than above e_int6 interrupt not changed set e_int5 clear e_int5 e_int5 bit setting 0 1 e_int5 interrupt cleared 1 0 e_int5 interrupt set other than above e_int5 interrupt not changed set e_int4 clear e_int4 e_int4 bit setting 0 1 e_int4 interrupt cleared 1 0 e_int4 interrupt set other than above e_int4 interrupt not changed set e_int3 clear e_int3 e_int3 bit setting 0 1 e_int3 interrupt cleared 1 0 e_int3 interrupt set other than above e_int3 interrupt not changed set e_int2 clear e_int2 e_int2 bit setting 0 1 e_int2 interrupt cleared 1 0 e_int2 interrupt set other than above e_int2 interrupt not changed set e_int1 clear e_int1 e_int1 bit setting 0 1 e_int1 interrupt cleared 1 0 e_int1 interrupt set other than above e_int1 interrupt not changed set e_int0 clear e_int0 e_int0 bit setting 0 1 e_int0 interrupt cleared 1 0 e_int0 interrupt set other than above e_int0 interrupt not changed
chapter 18 fcan controller user?s manual u14665ej2v0um 459 18.4.24 cann bus active register (cnba) the cnba register indicates frame information output via the can bus. this register is read-only, in 16-bit units. the c2ba register is valid only in models pd703079y and 70f3079y. after reset: 00ffh r addresses: c1ba: xxmffc5ah (m = 3, 7, b) c2ba: xxmffc9ah (m = 3, 7, b) 15 14 13 12 11 10 9 8 cnba 0 0 0 cact4 cact3 cact2 cact1 cact0 (n = 1, 2)76543210 tmno7 tmno6 tmno5 tmno4 tmno3 tmno2 tmno1 tmno0 cact4 cact3 cact2 cact1 cact0 can module status 0 0 0 0 0 reset state 0 0 0 0 1 bus idle wait 0 0 0 1 0 bus idle state 0 0 0 1 1 start of frame 0 0 1 0 0 standard identifier area 0 0 1 0 1 data length code area 0 0 1 1 0 data field area 0 0 1 1 1 crc field area 0 1 0 0 0 crc delimiter 01001ack slot 0 1 0 1 0 ack delimiter 0 1 0 1 1 end of frame area 0 1 1 0 0 intermission state 0 1 1 0 1 suspend transmission 0 1 1 1 0 error frame 0 1 1 1 1 error delimiter wait 1 0 0 0 0 error delimiter 10001bus off error 1 0 0 1 0 extended identifier area other than above setting prohibited tmno7 to tmno0 transmission message counter 0 to 31 message number of message awaiting transmission or being transmitted 32 to 254 not used 255 no messages awaiting transmission or being transmitted
chapter 18 fcan controller user?s manual u14665ej2v0um 460 18.4.25 cann bit rate prescaler register (cnbrp) the cnbrp register is used to set the transmission baud rate for the can module. use the cnbrp register to select the can protocol layer main system clock (f btl ). the baud rate is determined by the value set to the cnsync register. while in normal operating mode (cndef register?s mom bit = 0), writing to the cnbrp register is enabled only when the initialization mode has been set (cnctrl register?s init bit = 1). this register can be read/written in 16-bit units. the c2brp register is valid only in models pd703079y and 70f3079y. caution while in diagnostic processing mode (cndef register?s mom bit = 1), the cnbrp register can be accessed only when the initialization mode has been set.
chapter 18 fcan controller user?s manual u14665ej2v0um 461 (1/2) after reset: 0000h r/w addresses: c1brp: xxmffc5ch (m = 3, 7, b) c2brp: xxmffc9ch (m = 3, 7, b) (a) when tlm = 0 15 14 13 12 11 10 9 8 cnbrptlm0000000 (n = 1, 2)76543210 0 btype brp5 brp4 brp3 brp2 brp1 brp0 (b) when tlm = 1 15 14 13 12 11 10 9 8 cnbrptlm000000btype (n = 1, 2)76543210 brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 (a) when tlm = 0 tlm transfer layer mode specification 0 6-bit prescaler mode btype can bus type specification 0 low speed ( 125 kbps) 1 high speed (> 125 kbps) a brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer basic system clock (f btl ) 00 0 0 0 0 0f mem /2 10 0 0 0 0 1f mem /4 20 0 0 0 1 0f mem /6 30 0 0 0 1 1f mem /8 :f mem /{(a + 1) 2} 60111100f mem /122 61111101f mem /124 62111110f mem /126 63111111f mem /128 remark f btl = f mem /{(a + 1) 2}: can protocol layer basic system clock a = 0 to 63 (set by bits brp5 to brp0) f mem = can module clock
chapter 18 fcan controller user?s manual u14665ej2v0um 462 (2/2) (b) when tlm = 1 tlm transfer layer mode specification 1 8-bit prescaler mode btype can bus type specification 0 low speed ( 125 kbps) 1 high speed (> 125 kbps) a brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer basic system clock (f btl ) 000000000setting prohibited 100000001f mem /2 200000010f mem /3 300000011f mem /4 :f mem /(a + 1) 25211111100f mem /253 25311111101f mem /254 25411111110f mem /255 25511111111f mem /256 remark f btl = f mem /(a + 1): can protocol layer basic system clock a = 0 to 255 (set by bits brp7 to brp0) f mem = can module clock
chapter 18 fcan controller user?s manual u14665ej2v0um 463 18.4.26 cann bus diagnostic information register (cndinf) the cndinf register indicates all the can bus bits, including the stuff bits and delimiters. this information is used only for diagnostic purposes. because the number of bits starting from sof is added at each frame, the actual number of bits is the value obtained by subtracting the previous data. this register is read-only in 16-bit units. the c2dinf register is valid only in models pd703079y and 70f3079y. cautions 1. the cndinf register can be accessed only while in diagnostic processing mode (cndef register?s mom bit = 1) and in normal operating mode. in normal operating mode (cndef register?s mom bit = 0), this register cannot be accessed. 2. storage of the last 8 bits is automatically stopped if an error or a valid message (ack delimiter) is detected on the can bus. storage is automatically reset each time when sof is detected on the can bus. after reset: 0000h r addresses: c1dinf: xxmffc5ch (m = 3, 7, b) c2dinf: xxmffc9ch (m = 3, 7, b) 15 14 13 12 11 10 9 8 cndinf dinf15 dinf14 dinf13 dinf12 dinf11 dinf10 dinf9 dinf8 (n = 1, 2)76543210 dinf7 dinf6 dinf5 dinf4 dinf3 dinf2 dinf1 dinf0 dinfa can bus diagnostic information dinf15 to dinf8 number of bits starting from sof dinf7 to dinf0 information from last 8 bits
chapter 18 fcan controller user?s manual u14665ej2v0um 464 18.4.27 cann synchronization control register (cnsync) the cnsync register controls the data bit time for transmission speed. this register can be read/written in 16-bit units. the c2sync register is valid only in models pd703079y and 70f3079y. cautions 1. the cpu is able to read the cnsync register at any time. 2. writing to the cnsync register is enabled in initialization mode (when cnctrl register?s init bit = 1). 3. the limit values when setting the spta bit and dbta bit are as follows (a = 0 to 4). ? ? ? ? 5 btl spt (sampling point) 17 btl [4 spt4 to spt0 set values 16] ? ? ? ? 8 btl dbt (data bit time) 25 btl [7 dbt4 to dbt0 set values 24] ? ? ? ? sjw (synchronization jump width) < dbt ? spt ? ? ? ? 2 (dbt ? ? ? ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer basic system clock) (1/2) after reset: 0218h r/w addresses: c1sync: xxmffc5eh (m = 3, 7, b) c2sync: xxmffc9eh (m = 3, 7, b) 15 14 13 12 11 10 9 8 cnsync 0 0 0 samp sjw1 sjw0 spt4 spt3 (n = 1, 2)76543210 spt2 spt1 spt0 dbt4 dbt3 dbt2 dbt1 dbt0 samp bit sampling specification 0 sample data received at the sampling point once 1 sample received data three times and majority value used as sampled value sjw1 sjw0 synchronization jump width note 00btl 01btl 2 10btl 3 11btl 4 note as stipulated in can protocol specification ver. 2.0, part b. remark btl = 1/f btl (f btl : can protocol layer basic system clock)
chapter 18 fcan controller user?s manual u14665ej2v0um 465 (2/2) spt4 spt3 spt2 spt1 spt0 position of sampling point 00100btl 5 00101btl 6 00110btl 7 00111btl 8 01000btl 9 01001btl 10 01010btl 11 01011btl 12 01100btl 13 01101btl 14 01110btl 15 01111btl 16 10000btl 17 other than above setting prohibited sampling point within bit timing is selected. dbt4 dbt3 dbt2 dbt1 dbt0 data bit time 00111btl 8 01000btl 9 01001btl 10 01010btl 11 01011btl 12 01100btl 13 01101btl 14 01110btl 15 01111btl 16 10000btl 17 10001btl 18 10010btl 19 10011btl 20 10100btl 21 10101btl 22 10110btl 23 10111btl 24 11000btl 25 other than above setting prohibited 1-bit data length is set for can bus remark btl = 1/f btl (f btl : can protocol layer basic system clock)
chapter 18 fcan controller user?s manual u14665ej2v0um 466 18.5 cautions regarding bit set/clear function the fcan control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if values are written directly to these registers, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them. ? can global status register (cgst) ? can global interrupt enable register (cgie) ? cann control register (cnctrl) ? cann definition register (cndef) ? cann interrupt enable register (cnie) remark n = 1, 2 all 16 bits in the above registers can be read via the usual method. use the procedure described in figure 18-3 to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see figure 18-4 ). figure 18-3 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. figure 18-3. example of bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register? current values write values register? value after write operations
chapter 18 fcan controller user?s manual u14665ej2v0um 467 figure 18-4. 16-bit data during write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of clear n bit after bit set/clear operation 0 0 no change 01 0 10 1 1 1 no change remark n = 0 to 7
chapter 18 fcan controller user?s manual u14665ej2v0um 468 18.6 time stamp function the fcan controller supports a time stamp function. this function is needed to build a global time system. the time stamp function is implemented using a 16-bit free-running time stamp counter. two types of time stamp function can be selected for message reception in the fcan controller. use bit 3 (tmr) of the canx control register (cxctrl) to set the desired time stamp function (x = 1, 2). when the tmr bit is 0, the time stamp counter value is captured after the sof is detected on the can bus (see figure 18-5 ) and when the tmr bit is 1, the time stamp counter value is captured after the eof is detected on the can bus (a valid message is confirmed) (see figure 18-6 ). figure 18-5. time stamp function setting for message reception (when cxctrl register?s tmr bit = 0) <1> the time stamp counter value is captured to the temporary buffer when the sof is detected on the can bus. <2> a message is stored in can message buffer n and the value in the temporary buffer is copied to the m_timen register in can message buffer n when the eof is detected on the can bus. remark n = 00 to 31 x = 1, 2 message ack field eof sof <2> <1> time stamp counter temporary buffer m_timen can message buffer n
chapter 18 fcan controller user?s manual u14665ej2v0um 469 figure 18-6. time stamp function setting for message reception (when cxctrl register?s tmr bit = 1) <1> when the eof is detected on the can bus (a valid message is acknowledged), the captured time stamp counter value is copied to the m_timen register in can message buffer n when a message is stored in can message buffer n. remark n = 00 to 31 x = 1, 2 in a global time system, the time value must be captured using the sof. in addition, the ability to capture the time stamp counter value when message is stored in can message buffer n is useful for evaluating the fcan controller's performance. the captured time stamp counter value is stored in can message buffer n, so can message buffer n has its own time stamp function (n = 00 to 31). when the sof is detected on the can bus while transmitting a message, there is an option to replace the last two bytes of the message with the captured time stamp counter value by setting bit 5 (ats) of can message control register n (m_ctrln). this function can be selected for can message buffer n on a buffer by buffer basis. figure 18-7 shows the time stamp setting when the ats bit = 1. message ack field eof sof <1> time stamp counter m_timen can message buffer n
chapter 18 fcan controller user?s manual u14665ej2v0um 470 figure 18-7. time stamp function setting for message transmission (when m_ctrl register?s ats bit = 1) <1> the time stamp counter value is captured to the temporary buffer when the sof is detected on the can bus. <2> the value of the temporary buffer is added to the last 2 bytes of the data length code note specified by bits dlc3 to dlc0 of the m_dlcn register. note the ats bit of the m_ctrln register must be 1 and the data length must be more than 2 bytes to add the time stamp counter value to the transmit message. remark n = 00 to 31 table 18-12. example when adding captured time stamp counter value to last 2 bytes of transmit message data field dlc bit value note 1 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 1 m_datan0 register value ??????? 2 note 2 note 3 ?????? 3 m_datan0 register value note 2 note 3 ????? 4 m_datan0 register value m_datan1 register value note 2 note 3 ???? 5 m_datan0 register value m_datan1 register value m_datan2 register value note 2 note 3 ??? 6 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value note 2 note 3 ?? 7 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value note 2 note 3 ? 8 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value m_datan5 register value note 2 note 3 9 to 15 m_datan0 register value m_datan1 register value m_datan2 register value m_datan3 register value m_datan4 register value m_datan5 register value note 2 note 3 notes 1. see 18.4.1 can message data length registers 00 to 31 (m_dlc00 to m_dlc31) . 2. the lower 8 bits of the time stamp counter value when the sof is detected on the can bus 3. the higher 8 bits of the time stamp counter value when the sof is detected on the can bus remark n = 00 to 31 message ack field eof sof <2> <1> time stamp counter temporary buffer
chapter 18 fcan controller user?s manual u14665ej2v0um 471 18.7 message processing a modular system is used for the fcan controller. consequently, messages can be placed at any location within the message area. the messages can be linked to mask functions that are in turn linked to can modules. the fcan system is a multiplexed communication system. the priority of message transmission within this system is determined based on message identifiers (ids). to facilitate communication processing by application software when there are several messages awaiting transmission, the can module uses hardware to check the message ids and automatically determine whether or not linked messages are prioritized. this eliminates the need for software-based priority control. figure 18-8. example of message processing message number can module transmits messages in the following order. messages awaiting transmission id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 this auto priority control function can be canceled. when it is canceled, the priority among messages is determined based on the locations of the messages in memory (the message that has the lowest message number among the messages in the message buffer has the highest priority). when several messages have been received in the can module?s message buffers, priority control for storing received messages is as follows. priority rank 1: remote frame reception in the transmit message buffer. priority rank 2: non-masked message, for which m_statn register?s dn bit has not been set (1) priority rank 3: non-masked message, for which m_statn register?s dn bit has been set (1) priority rank 4: masked 0 message, for which m_statn register?s dn bit has not been set (1) priority rank 5: masked 0 message, for which m_statn register?s dn bit has been set (1) priority rank 6: masked 1 message, for which m_statn register?s dn bit has not been set (1) priority rank 7: masked 1 message, for which m_statn register?s dn bit has been set (1) priority rank 8: masked 2 message, for which m_statn register?s dn bit has not been set (1) priority rank 9: masked 2 message, for which m_statn register?s dn bit has been set (1) priority rank 10: masked 3 message, for which m_statn register?s dn bit has not been set (1) priority rank 11: masked 3 message, for which m_statn register?s dn bit has been set (1) remark n = 00 to 31 if priority based on location in memory is the same for multiple messages, the message buffer having the lowest message number is selected.
chapter 18 fcan controller user?s manual u14665ej2v0um 472 18.8 mask function a mask linkage function can be defined for each received message. this means that there is no need to distinguish between local masks and global masks. when the mask function is used, the received message?s identifier is compared with the message buffer?s identifier and the message can be stored in the defined message buffer regardless of whether the mask sets ?0? or ?1? as a result of the comparison. when the mask function is operating, a bit whose value is defined as ?1? by masking is not subject to the abovementioned comparison between the received message?s identifier and the message buffer?s identifier. however, this comparison is performed for any bit whose value is defined as ?0? by masking. for example, let us assume that all messages that have a standard-format id in which bit id27 to id25 = 0 and bits id24 and id22 = 1 are to be stored in message buffer 14 (which is linked by can module 1 or mask 1 as was explained in 18.4.6 ). the procedure for this example is shown below. <1> identifier bits to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx x = don?t care messages with id in which bits id27 to id25 = 0 and bits id24 and id22 = 1 are registered (initialized) in message buffer 14 (see 18.4.5 ). <2> identifier bits set to message buffer 14 (example) (using can message id registers l14 and h14 (m_idl14 and m_idh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 00001010000 id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 00000000000 id6 id5 id4 id3 id2 id1 id0 0000000 message buffer 14 is set as a standard-format identifier linked to mask 1 (see 18.4.6 ).
chapter 18 fcan controller user?s manual u14665ej2v0um 473 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 10000101111 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111 1: do not compare (mask) 0: compare values are written to mask 1 (see 18.4.18 ), bits cmid27 to cmid24 and cmid22 = 0 and bits cmid28, cmid23, and cmid21 to cmid0 = 1.
chapter 18 fcan controller user?s manual u14665ej2v0um 474 18.9 protocol fcan is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. the can specification is generally divided into two layers (physical layer and data link layer). in turn, the data link layer includes logical link control and medium access control. the composition of these layers is illustrated in figure 18-9 below. figure 18-9. composition of layers application layer physical layer data link layer logical link control (llc) medium access control (mac) not applicable message and status handling rules protocol rules signal level and bit expression rules higher lower 18.9.1 protocol mode function (1) standard format mode in this mode 2032 different identifiers can be set. the standard format mode uses 11-bit identifiers, which means that it can handle up to 2032 messages. (2) extended format mode this mode is used to extend the number of identifiers that can be set. ? while the standard format mode uses 11-bit identifiers, the extended format mode uses 29-bit (11 bits + 18 bits) identifiers which increases the number of messages that can be handled to 2032 2 18 messages. ? extended format mode is set when ?recessive (r): recessive in wired or? is set for both the srr and ide bits in the arbitration field. ? when an extended format mode message and a standard format mode remote frame are transmitted at the same time, the node that transmitted the extended format mode message is set to receive mode.
chapter 18 fcan controller user?s manual u14665ej2v0um 475 18.9.2 message formats four types of frames are used in can protocol messages. the output conditions for each type of frame are as follows. ? data frame: frame used for transmit data ? remote frame: frame used for transmit requests from receiving side ? error frame: frame that is output when an error has been detected ? overload frame: frame that is output when receiving side is not ready remark dominant (d): dominant in wired or recessive (r): recessive in wired or in the figure shown below, (d) = 0 and (r) = 1. (1) data frame and remote frame <1> data frame a data frame is the frame used for transmit data. this frame is composed of seven fields. figure 18-10. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8>
chapter 18 fcan controller user?s manual u14665ej2v0um 476 <2> remote frame a remote frame is transmitted when the receiving node issues a transmit request. a remote frame is similar to a data frame, except that the ?data field? is deleted and the rtr bit of the ?arbitration field? is recessive. figure 18-11. remote frame remark the data field is not transferred even if the control field?s data length code is not ?0000b?. (2) description of fields <1> start of frame (sof) the start of frame field is a 1-bit dominant (d) field that is located at the start of a data frame or remote frame. figure 18-12. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) ? the start of frame field starts when the bus line level changes. ? when ?dominant (d)? is detected at the sample point, reception continues. ? when ?recessive (r)? is detected at the sample point, bus idle mode is set. r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8>
chapter 18 fcan controller user?s manual u14665ej2v0um 477 <2> arbitration field the arbitration field is used to set the priority, data frame or remote frame, and protocol mode. this field includes an identifier, frame setting (rtr bit), and protocol mode setting bit. figure 18-13. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) figure 18-14. arbitration field (in extended format mode) note setting the higher 7 bits of the identifier as 1111111b is prohibited. cautions 1. id28 to id0 are identifier bits. 2. identifier bits are transferred in msb-first order. table 18-13. rtr frame settings frame type rtr bit data frame dominant remote frame recessive table 18-14. protocol mode setting and number of identifier (id) bits protocol mode srr bit ide bit no. of bits standard format mode none dominant (d) 11 bits extended format mode recessive (r) recessive (r) 29 bits r d r1 r0 rtr ide srr identifier note identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit)
chapter 18 fcan controller user?s manual u14665ej2v0um 478 <3> control field the control field sets ?n? as the number of data bytes in the data field (n = 0 to 8). r1 and r0 are fixed as dominant (d). the data length code bits (dlc3 to dlc0) set the byte count. remark dlc3 to dlc0: bits 3 to 0 in can message data length registers 00 to 31 (m_dlc00 to m_dlc31) (see 18.4.1 ) figure 18-15. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) in standard format mode, the arbitration field?s ide bit is the same bit as the r1 bit. table 18-15. data length code settings data length code dlc3 dlc2 dlc1 dlc0 data byte count 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no data field even if the data length code is not 0000b.
chapter 18 fcan controller user?s manual u14665ej2v0um 479 <4> data field the data field contains the amount of data set by the control field. up to 8 units of data can be set. remark data units in the data field are each 8 bits long and are ordered msb first. figure 18-16. data field r d data (8 bits) data (8 bits) data field (crc field) (control field) <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. it includes a 15-bit crc sequence and a 1-bit crc delimiter. figure 18-17. crc field ? the polynomial p(x) used to generate the 15-bit crc sequence is expressed as: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: no bit stuffing in start of frame, arbitration field, control field, or data field: the transferred crc sequence is calculated entirely from basic data bits. ? receiving node: the crc sequence calculated using data bits that exclude the stuffing bits in the receive data is compared with the crc sequence in the crc field. if the two crc sequences do not match, the node is passed to an error frame. r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field, control field)
chapter 18 fcan controller user?s manual u14665ej2v0um 480 <6> ack field the ack field is used to confirm normal reception. it includes a 1-bit ack slot and a 1-bit ack delimiter. figure 18-18. ack field ? the receiving node outputs the following depending on whether or not an error is detected between the start of frame field and the crc field. if an error is detected: ack slot = recessive (r) if no error is detected: ack slot = dominant (d) ? the transmitting node outputs two ?recessive(r)? bits and confirms the receiving node?s receive status. <7> end of frame (eof) the end of frame field indicates the end of transmission or reception. it includes 7 ?recessive(r)? bits. figure 18-19. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field)
chapter 18 fcan controller user?s manual u14665ej2v0um 481 <8> interframe space the interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next one. ? error active node when the bus is idle, transmit enable mode is set for each node. transmission then starts from a node that has received a transmit request. if the node is an error active node, the interframe space is composed of a 3- or 2-bit intermission field and bus idle field. ? error passive node after an 8-bit bus idle field, transmit enable mode is set. receive mode is set if a transmission starts from a different node during bus idle mode. the error passive node is composed of an intermission field, suspend transmission field, and bus idle field. figure 18-20. interframe space (a) error active r d interframe space intermission (3 or 2 bits) bus idle (0 or more bits) (frame) (frame) (b) error passive r d interframe space intermission (3 or 2 bits) suspend transmission (8 bits) bus idle (0 or more bits) (frame) (frame) ? bit length of intermission when transmission is pending, transmission is resumed after a 3-bit intermission. when receiving, the receive operation starts after only two bits. ? bus idle this mode is set when no nodes are using any buses. ? suspend transmission this is an 8-bit recessive (r) field that is transmitted from a node that is in error passive mode.
chapter 18 fcan controller user?s manual u14665ej2v0um 482 table 18-16. operation when third bit of intermission is ?dominant (d)? transmit status operation no pending transmissions a receive operation is performed when start of frame output by other node is detected. pending transmission exists the identifier is transmitted when start of frame output by local node is detected. <9> error frame an error frame is used to output from a node in which an error has been detected. when a passive error flag is being output, if there is ?dominant (d)? output from another node, the passive error flag does not end until 6 consecutive bits are detected on the same level. if the bit following the 6 consecutive ?recessive (r)? bits is ?dominant (d)?, the error frame ends when the next ?recessive (r)? bit is detected. figure 18-21. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag error flag error bit error frame no name bit count definition error active node consecutive output of 6 ?dominant (d)? bits <1> error flag 6 error passive node consecutive output of 6 ?recessive (r)? bits <2> error flag 0 to 6 a node that receives an error flag is a node in which bit stuffing errors are detected, after which an error flag is output. <3> error delimiter 8 8 consecutive ?recessive (r)? bits are output. if a ?dominant (d)? bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> error bit ? this bit is output following the bit where an error occurred. if the error is a crc error, it is output following an ack delimiter. <5> interframe space or overload frame 3/10 20 max. an interframe space or overload frame starts from here.
chapter 18 fcan controller user?s manual u14665ej2v0um 483 <10> overload frame an overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. if a bit error is detected during intermission mode, it is output starting from the bit following the bit where the bit error was detected. figure 18-22. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame no name bit count definition <1> overload flag starting from node m 6 consecutive output of 6 ?dominant (d)? bits. output when node m is not ready to receive. <2> overload flag starting from node n 0 to 6 node n, which has received an overload flag in the interframe space, outputs an overload flag <3> overload delimiter 8 8 consecutive ?recessive (r)? bits are output. if a ?dominant (d)? bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space or overload frame 3/10 20 max. an interframe space or overload frame starts from here. remark n m
chapter 18 fcan controller user?s manual u14665ej2v0um 484 18.10 functions 18.10.1 determination of bus priority (1) when one node has starting transmitting ? in bus idle mode, the node that outputs data first starts transmitting. (2) when several nodes have started transmitting ? the node that has the longest string of consecutive ?dominant (d)? bits starting from the first bit in the arbitration field has top priority for bus access (?dominant (d)? bits take precedence due to wired or bus arbitration). ? the transmitting node compares the arbitration field which it has output and the bus data level table 18-17. determination of bus priority matched levels transmission continues mismatched levels when a mismatch is detected, data output stops at the next bit, and the operation switches to reception. (3) priority between data frame and remote frame ? if a bus conflict occurs between a data frame and a remote frame, the data frame takes priority because its last bit (rtr) is ?dominant (d)?. 18.10.2 bit stuffing bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for at least five consecutive bits. table 18-18. bit stuffing transmit when transmitting data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and crc fields, one bit of data whose level is inverted from the previous level is inserted before the next bit. receive when receiving data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and crc fields, the next bit of data is deleted before reception is resumed. 18.10.3 multiple masters since bus priority is determined based on the identifier, any node can be used as the bus master. 18.10.4 multi-cast even when there is only one transmitting node, the same identifier can be set for several nodes, so that the same data can be received by several nodes at the same time.
chapter 18 fcan controller user?s manual u14665ej2v0um 485 18.10.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function can be used to set the fcan controller to sleep (standby) mode to reduce power consumption. the can sleep mode is set via the procedure stipulated in the can specifications. the can sleep mode can be set to wake up by the bus operation, however the can stop mode cannot be set to wake up by bus operation (this is controlled via cpu access). 18.10.6 error control function (1) types of errors table 18-19. types of errors description of error detected status error type detection method detection condition transmit/ receive field/frame bit error comparison of output level and bus level (excludes stuff bits) mismatch between levels transmitting/ receiving nodes bits outputting data on bus in start of frame to end of frame, error frame, or overload frame stuff error use stuff bits to check receive data six consecutive bits of same-level data transmitting/ receiving nodes start of frame to crc sequence crc error comparison of crc generated from receive data and received crc sequence crc mismatch receiving node start of frame to data field form error check fixed-format field/frame detection of inverted fixed format receiving node ? crc delimiter ? ack field ? end of frame ? error frame ? overload frame ack error use transmitting node to check ack slot use ack slot to detect recessive transmitting node ack slot (2) error frame output timing table 18-20. error frame output timing error type output timing bit error, stuff error, form error, ack error error frame is output at the next bit following the bit where error was detected crc error error frame is output at the next bit following the ack delimiter (3) handling of errors the transmitting node retransmits the data frame or remote frame after the error frame has been transmitted.
chapter 18 fcan controller user?s manual u14665ej2v0um 486 (4) error statuses (a) types of error statuses the three types of error statuses are listed below. error active error passive bus off ? the error status is controlled by the transmit error counter and receive error counter (see 18.4.22 cann error count register (cnerc) ). ? the various error statuses are categorized according to their error counter values. ? the error flags used for error statuses differ between transmit and receive operations. ? when the error counter value reaches 96 or more, the bus status must be tested since the bus may become seriously damaged. ? during start-up, if only one node is active, the error frame and data are repeatedly re-sent because no ack is returned even data has been transmitted. in such cases, bus off mode cannot be set. even if the transmitting node that is sending the transmit message repeatedly experiences an error status, bus off mode cannot be set. table 18-21. types of error statuses error status type operation error counter value type of output error flag error active transmit/ receive 0 to 127 active error flag (6 consecutive ?dominant (d)? bits) transmit 128 to 255 error passive receive 128 or more passive error flag (6 consecutive ?recessive (r)? bits) bus off transmit 256 or more transfer is not possible. when a string of at least 11 consecutive ?recessive (r)? bits occurs 128 times, the error counter is zero-cleared and error active status can be resumed.
chapter 18 fcan controller user?s manual u14665ej2v0um 487 (b) error counter the error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. the count up/count down timing occurs at the first bit of the error delimiter. table 18-22. error counter status transmit error counter (tec7 to tec0) receive error counter (rec7 to rec0) when receiving node has detected an error (except for bit errors that occur in an active error flag or overload flag) no change +1 when ?dominant (d)? is detected following error frame?s overload flag output by the receiving node no change +8 when transmitting node has sent an error flag [when error counter = 0] <1> when an ack error was detected in error passive status and a ?dominant (d)? was not detected during error flag output <2> when a stuff error occurs in the arbitration field +8 no change detection of bit error during output of active error flag or overload flag (transmitting node with error active status) +8 no change detection of bit error during output of active error flag or overload flag (receiving node with error active status) no change +8 when 14 consecutive ?dominant (d)? bits were detected from the start of each node?s active error flag or overload flag, followed by detection of eight consecutive dominant bits. each node has detected eight consecutive dominant bits after a passive error flag. +8 +8 the transmitting node has completed a transmit operation without any errors ( 0 if error counter value is 0). ?1 no change the receiving node has completed a receive operation without any errors. no change ?? 1 (1 rec7 to rec0 127) ? 0 (rec7 to rec0 = 0) ? 127 is set (rec7 to rec0 > 127) (c) occurrence of bit error during intermission in this case, an overload frame occurs. caution when an error occurs, error control is performed according to the contents of the transmitting and receiving error counters as they existed prior to the error?s occurrence. the error counter value is incremented only after an error flag has been output.
chapter 18 fcan controller user?s manual u14665ej2v0um 488 18.10.7 baud rate control function (1) prescaler the v850/sf1 includes a prescaler for dividing the can module clock (f mem ). this prescaler generates a clock (f btl ) that is based on a division ratio ranging from 2 to 128 applied to the system clock when the cnbrp register?s tlm bit = 0, and from 2 to 256 when the tlm bit = 1 (see 18.4.25 cann bit rate prescaler register (cnbrp) ). (2) nominal bit time (8 to 25 time quantum) the definition of 1 data bit time is shown below. remark 1 time quantum = 1/f btl figure 18-23. nominal bit time nominal bit time sjw sjw phase segment 2 phase segment 1 sample point prop segment sync segment segment name segment length description sync segment (synchronization segment) 1 this segment begins when resynchronization occurs. prop segment (propagation segment) 1 to 8 (programmable) this segment is used to absorb the delays caused by the output buffer, can bus, and input buffer. it is set to return an ack signal until phase segment 1 begins. prop segment time (output buffer delay) + (can bus delay) + (input buffer delay) phase segment 1 (phase buffer segment 1) 1 to 8 (programmable) phase segment 2 (phase buffer segment 2) maximum value from phase segment 1, ipt note (ipt = 0 to 2) this segment is used to compensate for errors in the data bit time. it accommodates a wide margin or error but slows down communication speed. sjw (resynchronization jump width) 1 to 4 (programmable) this sets the range for bit synchronization. note ipt: information processing time
chapter 18 fcan controller user?s manual u14665ej2v0um 489 (3) data bit synchronization ? since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. ? as for the transmitting node, data is transmitted in sync with the transmitting node?s bit timing. (a) hardware synchronization this is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode. ? when a falling edge is detected on the bus, the current bit is assigned to the sync segment and the next bit is assigned to the prop segment. in such cases, synchronization is performed regardless of the sjw. ? since bit synchronization must be established after a reset or after a wake-up, hardware synchronization is performed only at the first level change that occurs on the bus (for the second and subsequent level changes, bit synchronization is performed as shown below). figure 18-24. coordination of data bit synchronization phase segment 2 phase segment 1 prop segment sync segment start of frame bus idle can bus bit timing
chapter 18 fcan controller user?s manual u14665ej2v0um 490 (b) resynchronization resynchronization is performed when a level change is detected on the bus during a receive operation. ? the edge?s phase error is produced by the relative positions of the detected edge and sync segment. 0: when edge is within sync segment positive: edge is before sample point (phase error) negative: edge is after sample point (phase error) ? when the edge is detected as within the bit timing specified by the sjw, synchronization is performed in the same way as hardware synchronization. ? when the edge is detected as extending beyond the bit timing specified by the sjw, synchronization is performed on the following basis. when phase error is positive: phase segment 1 is lengthened to equal the sjw when phase error is negative: phase segment 2 is shortened to equal the sjw ? a ?shifting? of the baud rate for the transmitting and receiving nodes moves the relative position of the sample point for data on the receiving node. figure 18-25. resynchronization phase segment 2 phase segment 1 prop segment sync segment sof next bit previous bit can bus bit timing sjw
chapter 18 fcan controller user?s manual u14665ej2v0um 491 18.11 operations 18.11.1 initialization processing figure 18-26 shows a flowchart of initialization processing. the register setting flow is shown in figures 18-27 to 18-38. figure 18-26. initialization processing start set can main clock selection register (cgcs) : see setting shown in figure 18-27 setting of can main clock select register (cgcs) : see setting shown in figure 18-28 setting of can global interrupt enable register (cgie) : see setting shown in figure 18-29 setting of can global status register (cgst) : see setting shown in figure 18-30 setting of cann bit rate prescaler (cnbrp) : see setting shown in figure 18-31 setting of cann synchronization control register (cnsync) : see setting shown in figure 18-32 setting of cann interrupt enable register (cnie) : see setting shown in figure 18-33 setting of cann definition register (cndef) : see setting shown in figure 18-34 setting of cann control register (cnctrl) : see figure 18-35 setting of cann address mask a registers l and h (cnmaskla and cnmaskha) : see figure 18-36 message buffer setting set can global interrupt enable register (cgie) set can global status register (cgst) set cann bit rate prescaler (cnbrp) set init = 1 (cnctrl) set cann synchronization control register (cnsync) set cann interrupt enable register (cnie) set cann definition register (cndef) set cann control register (cnctrl) mask required for message id? set message buffer (repeat as many times as number of messages) clear init = 1 (cnctrl) istat = 0? (cnctrl) end yes yes yes no no no istat = 1? (cnctrl) set mask (cnmaska) remark a = 0 to 3 n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 492 figure 18-27. setting of can main clock select register (cgcs) start f mem f gts1 f gts select clock for memory access controller (mcp0 to mcp3) f mem = f mem1 / (n + 1) n = 0 to 15 (set using bits mcp0 to mcp3) f gts = f gts1 / (n + 1) n = 0 to 255 (set using bits cgts0 to cgts7) gtcs1, gtcs0 = 00: f gts1 = f mem /2 gtcs1, gtcs0 = 01: f gts1 = f mem /4 gtcs1, gtcs0 = 10: f gts1 = f mem /8 gtcs1, gtcs0 = 11: f gts1 = f mem /16 select global timer clock (gtcs0, gtcs1) select system timer prescaler (cgts0 to cgts7) remark f mem = can module clock f mem1 = f xx : main system clock f gts1 = global timer clock f gts = system timer prescaler figure 18-28. setting of can global interrupt enable register (cgie) start no enable interrupt for g_ie1 bit yes set g_ie1 = 1 clear g_ie1 = 0 no enable interrupt for g_ie2 bit ? interrupt occurs if memory address in undefined area is accessed. ? interrupt occurs if the gom bit is not cleared (0) under the following conditions. ? when shutdown is disabled (efsd bit = 0). ? when a can module not in the initialization status (istat bit = 0) exists. ? interrupt occurs if invalid write operation is performed when the gom bit = 1, such as in temp buffer. ? interrupt occurs if can module register (with name starting with cn (n = 1, 2)) is accessed when the gom bit = 0. yes set g_ie2 = 1 clear g_ie2 = 0 remark gom: bit of can global status register (cgst) efsd: bit of can global status register (cgst) istat: bit of cann control register (cnctrl)
chapter 18 fcan controller user?s manual u14665ej2v0um 493 figure 18-29. setting of can global status register (cgst) start no use time stamp function? yes set tsm = 1 clear tsm = 0 start fcan operation set gom = 1 clear gom = 0 figure 18-30. setting of cann bit rate prescaler register (cnbrp) remarks 1. f btl = can protocol layer basic system clock f mem = can module clock 2 .n = 1, 2 start no transfer speed is 125 kbps or less yes btype = 0 (low speed) f btl setting when tlm = 0 brp5 to brp0 when tlm = 1 brp7 to brp0 when tlm = 0 f btl = f mem /{(m + 1) 2} m = 0 to 63 (set using bits brp5 to brp0) when tlm = 1 f btl = f mem /(m + 1) m = 0 to 255 (set using bits brp7 to brp0) f btl btype = 1 (high speed)
chapter 18 fcan controller user?s manual u14665ej2v0um 494 figure 18-31. setting of cann synchronization control register (cnsync) start no samp = 0 set data bit time (dbt4 to dbt0) 1 bit time = btl (m + 1) m = 7 to 24 (set using bits dbt4 to dbt0) sampling point = btl (m + 1) m = 4 to 16 (set using bits spt4 to spt0) set sampling point (spt4 to spt0) set sjw (sjw1, sjw0) samp = 1 yes set once-only (single shot) sampling set sampling for one location only set sampling for three locations sjw = btl ( m + 1) m = 0 to 3 (set using bits sjw1 and sjw0) remarks 1. btl = 1/f btl (f btl = can protocol layer basic system clock) 2. n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 495 figure 18-32. setting of cann interrupt enable register (cnie) set e_int0 = 1 clear e_int0 = 0 start no yes yes yes yes yes yes yes clear e_int0 = 1 set e_int0 = 0 enable interrupt for e_int0? interrupt enable flag for end of transmission set e_int1 = 1 clear e_int1 = 0 no clear e_int1 = 1 set e_int1 = 0 enable interrupt for e_int1? interrupt enable flag for end of reception set e_int2 = 1 clear e_int2 = 0 no clear e_int2 = 1 set e_int2 = 0 enable interrupt for e_int2? interrupt enable flag for error passive or bus off by tec set e_int3 = 1 clear e_int3 = 0 no clear e_int3 = 1 set e_int3 = 0 enable interrupt for e_int3? interrupt enable flag for error passive by rec set e_int4 = 1 clear e_int4 = 0 no clear e_int4 = 1 set e_int4 = 0 enable interrupt for e_int4? interrupt enable flag for wake-up from can sleep mode set e_int5 = 1 clear e_int5 = 0 no clear e_int5 = 1 set e_int5 = 0 enable interrupt for e_int5? interrupt enable flag for can bus error set e_int6 = 1 clear e_int6 = 0 no clear e_int6 = 1 set e_int6 = 0 enable interrupt for e_int6? interrupt enable flag for can error remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 496 figure 18-33. setting of cann definition register (cndef) set mom = 1 clear mom = 0 start no yes yes yes yes clear mom = 1 set mom = 0 set to diagnostic processing mode? normal operating mode normal operation mode transmit priority is determined based on message numbers diagnostic processing mode transmit priority is determined based on identifiers single-shot mode: transmit only once. do not retransmit. clear dgm = 1 set dgm = 0 no set dgm = 1 clear dgm = 0 store to buffer used for diagnostic processing mode note ? clear pbb = 1 set pbb = 0 no set pbb = 1 clear pbb = 0 determine transmit priority based on identifiers? set ssht = 1 clear ssht = 0 no clear ssht = 1 set ssht = 0 set single-shot mode? note bits 5 to 3 (mt2 to mt0) in can message configuration register m (m_confm) are set to ?111? remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 497 figure 18-34. setting of cann control register (cnctrl) remark n = 1, 2 start yes clear tmr = 1 set tmr = 0 store timer value at sof? set time stamp for receiving set overwrite for receive message buffer set dominant level for transmit pins set dominant level for receive pins store timer value at eof do not overwrite message in dn flag (delete new message) set dominant level to high level set dominant level to high level set ovm = 1 clear ovm = 0 yes clear ovm = 1 set ovm = 0 store message of dn flag? set dlevt = 1 clear dlevt = 0 yes clear dlevt = 1 set dlevt = 0 set dominant level to low level? set dlevr = 1 clear dlevr = 0 yes no no no no clear dlevr = 1 set dlevr = 0 set dominant level to low level? set tmr = 1 clear tmr = 0
chapter 18 fcan controller user?s manual u14665ej2v0um 498 figure 18-35. setting of cann address mask a registers l and h (cnmaskla and cnmaskha) start standard frame mask setting for standard frame (x = 18 to 28) mask setting for extended frame (x = 0 to 28) mask setting for message id format yes cmidx = 0 cmidy = 1 cmidx = 1 mask id bit? no yes no yes cmide = 0 cmide = 1 check id type? no yes cmidx = 0 cmidx = 1 mask id bit? no (y = 0 to 17)
chapter 18 fcan controller user?s manual u14665ej2v0um 499 figure 18-36. message buffer setting start no standard frame? set message id type yes ide = 0 (standard) (m_idhm) set message configuration see figure 18-37 setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31) see figure 18-38 setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) ide = 1 (extended) (m_idhm) set identifier (standard, extended) set message control byte set message length remark m = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 500 figure 18-37. setting of can message configuration registers 00 to 31 (m_conf00 to m_conf31) start use message buffer? release can message buffer yes yes ma2 to ma0 = 000 ma2 to ma0 = 010 ma2 to ma0 = 001 yes no no no no no no no mt2 to mt0 = 111 (used in diagnostic processing mode) mt2 to mt0 = 000 mt2 to mt0 = 001 mt2 to mt0 = 010 mt2 to mt0 = 011 mt2 to mt0 = 100 mt2 to mt0 = 101 can module2 message buffer address specification can module1 yes yes yes yes transmit message receive message (no mask setting) receive message (set mask 0) receive message (set mask 1) receive message (set mask 2) receive message (set mask 3)
chapter 18 fcan controller user?s manual u14665ej2v0um 501 figure 18-38. setting of can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) start yes no no rtr = 0 rtr = 1 transmit/receive remote frame transmit/receive data frame? set remote frame auto acknowledge function yes no ie = 0 ie = 1 enable interrupt disable interrupt? yes no rmde0 = 1 rmde0 = 0 remote frame auto acknowledge? yes no rmde1 = 1 rmde1 = 0 ats = 1 ats = 0 set dn flag? yes apply time stamp? set dn flag when remote frame is received
chapter 18 fcan controller user?s manual u14665ej2v0um 502 18.11.2 transmit setting transmit messages are output from the target message buffer. figure 18-39. transmit setting start end of transmit operation set rdy flag set rdy = 1, clear rdy = 0 (sc_statm) set data (m_datamn) select transmit message buffer set transmit request flag set trq = 1, clear trq = 0 (sc_statm) remark n = 0 to 7 m = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 503 18.11.3 receive setting receive messages are retrieved from the target message buffer. figure 18-40. receive setting start confirm end of reception (reception completion interrupt or reception completion interrupt pending flag) set rdy flag set rdy = 1, clear rdy = 0 (sc_statn) end of receive operation yes receive data frame no yes receive data frame? receive remote frame : detection methods <1> detect using cann information register (cnlast) <2> detect using can message search start/result register (cgmss/cgmsr) no dn = 0 (m_statm) detect target message buffer clear dn flag clear dn = 1, set dn = 0 (sc_statm) get data length transmit operation get data get time stamp remark m = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 504 18.11.4 can sleep mode in can sleep mode, the fcan controller can be set to standby mode. a wake-up occurs when there is a bus operation. figure 18-41. can sleep mode setting start end of can sleep mode setting no yes sleep = 1 (cnctrl) set sleep = 1 clear sleep = 0 (cnctrl) remark n = 1, 2 figure 18-42. clearing of can sleep mode by can bus active status start can bus active sleep = 0 (cnctrl) wake = 1 (cndef) wake-up interrupt occurs end of can sleep mode clearing operation remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 505 figure 18-43. clearing of can sleep mode by cpu clear sleep = 1 set sleep = 0 (cnctrl) sleep = 0 (cnctrl) start end of can sleep mode clearing operation remark n = 1, 2
chapter 18 fcan controller user?s manual u14665ej2v0um 506 18.11.5 can stop mode in can stop mode, the fcan controller can be set to standby mode. no wake-up occurs when there is a bus operation (stop mode is controlled by cpu access only). figure 18-44. can stop mode setting remark n = 1, 2 figure 18-45. clearing of can stop mode start end of can stop mode setting yes sleep = 1 (cnctrl) no set stop = 1 clear stop = 0 (cnctrl) set can sleep mode (see figure 18-41 ) start end of can stop mode clearing operation clear stop = 1 set stop = 0 clear sleep = 1 set sleep = 0 (cnctrl)
chapter 18 fcan controller user?s manual u14665ej2v0um 507 18.12 rules for correct setting of baud rate the can protocol limit values for ensuring correct operation of fcan are described below. if these limit values are exceeded, a can protocol violation may occur, which can result in operation faults. always make sure that settings are within the range of limit values. (a) 5 btl spt (sampling point) 17 btl [4 spt4 to spt0 set values 16] (b) 8 btl dbt (data bit time) 25 btl [7 dbt4 to dbt0 set values 24] (c) sjw (synchronization jump width) < dbt ? spt (d) 2 (dbt ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer basic system clock) spt4 to spt0 (bits 9 to 5 of cann synchronization control register (cnsync)) dbt4 to dbt0 (bits 4 to 0 of cann synchronization control register (cnsync)) (1) example of fcan baud rate setting (when cnbrp register?s tlm bit = 0) the following is an example of how correct settings for the cnbrp register and cnsync register can be calculated. conditions from can bus: <1> can module frequency (f mem ): 16 mhz <2> can bus baud rate: 83 kbps <3> sampling point: 75% or more <4> sjw: 3 btl first, calculate the ratio between the can module frequency and the can bus baud rate frequency as shown below. f mem / can bus baud rate = 16 mhz / 83 khz 192.77 2 6 3 set an even number between 2 and 128 to the cnbrp register?s bits brp5 to brp0 as the setting for the prescaler (can protocol layer basic system clock: f btl ), then set a value between 8 and 25 to the cnsync register?s bits dtb4 to dbt0 as the data bit time. since it is assumed that the sjw value is 3, the maximum setting value for spt (sampling point) is 4 less than the data bit time setting and is less than 17. (spt dbt ? 4 and spt 17)
chapter 18 fcan controller user?s manual u14665ej2v0um 508 given the above limit values, the following 3 settings are possible. prescaler dbt spt (max.) calculated spt 16 12 8 8/12 = 67% 12 16 12 12/16 = 75% 8 24 17 17/24 = 71% 16 mhz/83 kbps ? 192 = 64 3<1> = 48 4<2> = 32 6<3> = 24 8<4> = 16 12 <5> = 12 16 <6> = 8 24 <7> = 6 32 <8> = 4 48 <9> = 3 64 <10> the settings that can actually be made for the v850/sf1 are in the range from <5> to <7> above (the section enclosed in broken lines). among these options in the range from <5> to <7> above, option <6> is the ideal setting for used when actually setting the register. (i) prescaler (can protocol layer basic system clock: f btl ) setting f btl is calculated as below. ? f btl = f mem /{(a + 1) 2} : [0 a 63] value a is set using bits 5 to 0 (brp5 to brp0) of the cnbrp register. f btl = 16 mhz/12 = 16 mhz/{(5 + 1) 2} thus a = 5 therefore, cnbrp register = 0005h
chapter 18 fcan controller user?s manual u14665ej2v0um 509 (ii) dbt (data bit time) setting dbt is calculated as below. ? dbt = btl (a + 1) : [7 a 24] value a is set using bits 4 to 0 (dbt4 to dbt0) of the cnsync register. dbt = btl 16 = btl (a + 1) thus a = 15 therefore, cnbrp register?s bits dbt4 to dbt0 = 01111b note that 1/dbt = f btl /16 ? 1333 khz/16 ? 83 kbps (nearly equal to the can bus baud rate) (iii) spt (sampling point) setting given sjw = 3: sjw < dbt ? spt 3 < 15 ? spt spt < 12 therefore, spt is set as 11 (max.) spt is calculated as below. ? spt = btl (a + 1) : [4 a 16] value a is set using bits 9 to 5 (spt4 to spt0) of the cnsync register. spt = btl 12 = btl (11 + 1) thus a = 11 (iv) sjw (synchronization jump width) setting sjw is calculated as below. ? sjw = btl (a + 1) : [0 a 3] value a is set using bits11 and 10 (sjw1, sjw0) of the cnsync register. cnsync register?s bits sjw1 and sjw0 = btl 3 = btl (2 + 1) thus a = 2 the cnsync register settings based on these results are shown in figure 18-46 below.
chapter 18 fcan controller user?s manual u14665ej2v0um 510 figure 18-46. cnsync register settings 15 14 13 12 11 10 9 8 cnsync 0 0 0 samp sjw1 sjw0 spt4 spt3 setting00001001 76543210 spt2 spt1 spt0 dbt4 dbt3 dbt2 dbt1 dbt0 setting01101111 18.13 prioritization of message buffers during receive comparison several message buffers can be built for receiving messages. in such cases, a system of prioritization in receiving messages must be established for these message buffers. 18.13.1 reception of data frames table 18-23. prioritization of message buffers when receiving data frames priority ranking description 1 (high) receive messages can be stored in receive message buffers when the receive messages meet the following conditions. <1> messages are not linked to masks <2> m_statn register?s dn bit has not been set (1) (n = 00 to 31) if several messages have met the above conditions, the message buffer having the lowest message number is selected. 2 receive messages can be stored in receive message buffers when the receive messages meet the following conditions. <1> messages are not linked to masks <2> m_statn register?s dn bit has been set (1) (n = 00 to 31) if several messages have met the above conditions, the message buffer having the lowest message number is selected. 3 (low) receive messages can be stored in receive message buffers that are linked to ma sks. however, the following conditions must be met. <1> if several receive message buffers are linked to ma sks, the mess age buffer will be selected based on the mask number assigned to it. the lowest mask number takes the highest priority. <2> if several message buffers meet the conditions mentioned in ?<1>? above, the message buffer is selected based on its dn bit (in the m_statn register). a message buffer in which this bit is not set (1) takes priority over a message buffer in which this bit is set (1). <3> if several message buffers meet the conditions mentioned in ?<1>? and ?<2>? above, the message buffer with the lowest message number is selected.
chapter 18 fcan controller user?s manual u14665ej2v0um 511 18.13.2 reception of remote frames table 18-24. prioritization of message buffers when receiving remote frames priority ranking description 1 (high) receive messages can be stored in transmit message buffers when the receive messages meet the following conditions. ? messages are not linked to masks if several transmit message buffers have met the above conditions, the message buffer having the lowest message number is selected. 2 receive messages can be stored in receive message buffers when the receive messages meet the following conditions. ? messages are not linked to masks ? m_statn register?s dn bit has not been set (1) (n = 00 to 31) if several receive message buffers have met the above conditions, the message buffer having the lowest message number is selected. 3 receive messages can be stored in receive message buffers when the receive messages meet the following conditions. ? messages are not linked to masks ? m_statn register?s dn bit has been set (1) (n = 00 to 31) if several receive message buffers have met the above conditions, the message buffer having the lowest message number is selected. 4 (low) receive messages can be stored in receive message buffers that are linked to ma sks. however, the following conditions must be met. <1> if several receive message buffers are linked to ma sks, the mess age buffer will be selected based on the mask number assigned to it. the lowest mask number takes the highest priority. <2> if several message buffers meet the conditions mentioned in ?<1>? above, the message buffer is selected based on its dn bit (in the m_statn register). (n = 00 to 31) a message buffer in which this bit is not set (1) takes priority over a message buffer in which this bit is set (1). <3> if several message buffers meet the conditions mentioned in ?<1>? and ?<2>? above, the message buffer with the lowest message number is selected.
chapter 18 fcan controller user?s manual u14665ej2v0um 512 18.14 ensuring data consistency when the cpu reads data from can message buffers, it is essential for the read data to be consistent. two methods are used to ensure data consistency: sequential data read and burst mode data read. 18.14.1 sequential data read when the cpu performs sequential access of a message buffer, data is read from the buffer in the order shown in figure 18-47 below. only the fcan can set the m_statn register?s dn bit (1) and only the cpu can clear it (0), so during the read operation the cpu must be able to check whether or not any new data has been stored in the message buffer. figure 18-47. sequential data read read cpu end of cpu s read operation yes dn = 0 (m_statn) no dn = 0 (m_statn) read data from message buffer remark n = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 513 18.14.2 burst read mode burst read mode is implemented in the fcan to enable faster access to complete messages and secure the synchrony of data. burst read mode starts up automatically each time the cpu reads the m_dlcn register and data is then copied from the message buffer area to a temporary read buffer. data continues to be read from the temporary buffer as long as the cpu keeps directly incrementing (+1) the read address (in other words, when data is read in the following order: m_dlcn register m_ctrln register m_timen register m_datan0 to m_datan7 registers m_idln, m_idhn register). if these linear address rules are not followed or if access is attempted to an address that is lower than the m_idhn register?s address (such as the m_confn register or m_statn register), burst read mode becomes invalid. caution 16-bit read access is required for the entire message buffer area when using the burst read mode. if 8-bit access (byte read operation) is attempted, burst read mode does not start up even if the address is linearly incremented (+1) as described above. remark n = 00 to 31
chapter 18 fcan controller user?s manual u14665ej2v0um 514 18.15 interrupt conditions 18.15.1 interrupts that occur for fcan controller when interrupts are enabled (condition <1>: the m_ctrlm register?s ie bit = 1, conditions other than <1>: c_ie register?s interrupt enable flag = 1), interrupts will occur under the following conditions (m = 00 to 31). <1> message-related operation has succeeded ? when a message has been received in the receive message buffer ? when a remote frame has been received in the transmit message buffer (only when auto acknowledge mode has not been set, i.e., when the m_ctrlm register?s rmde0 bit = 0) ? when a message has been transmitted from the transmit message buffer <2> when a can bus error has been detected ? bit error ? bit stuff error ? form error ? crc error ? ack error <3> when the can bus mode has been changed ? error passive status elapsed while fcan was transmitting ? bus off status was set while fcan was transmitting ? error passive status elapsed while fcan was receiving <4> internal error ? overrun error 18.15.2 interrupts that occur for global can interface interrupts occur for the global can interface under the following conditions. ? access to undefined area ? when clearing (0) of the gom bit is attempted with the efsd bit of the cgst register = 0, when there is even one can module not initialized (istat bit of cnctrl register = 0) ? access to the can module register (register name starting with ?cn? (n = 1, 2)), when the gom bit of the cgst register = 0 ? access to a temporary buffer when the gom bit of the cgst register = 1 (area after address of cnsync register)
chapter 18 fcan controller user?s manual u14665ej2v0um 515 18.16 how to shut down fcan controller the following procedure should be used to stop can bus operations in order to stop the clock supply to the can interface (to set low power mode). <1> set fcan controller initialization mode ? set initialization mode (init bit = 1 in cnctrl register (set init bit = 1, clear init bit = 0)) (n = 1, 2) <2> stop time stamp counter ? set tsm bit = 0 in cgst register (set tsm bit = 0, clear tsm bit = 1) <3> stop can interface ? set gom bit = 0 in cgst register (set gom bit = 0, clear gom bit = 1) ? stop can clock cautions 1. if the above procedure is not performed correctly, the can interface (in active status) can cause operation faults. 2. perform only steps <1> and <2> above when setting the cpu itself to low power mode and operating the can interface using a cpu-supplied clock. in this case, stopping the can interface clock (step <3> above) is automatically performed when the cpu clock is stopped, so there is no need to perform step <3>. 18.17 cautions on use <1> bit manipulation is prohibited for all fcan controller registers. <2> be sure to properly clear (0) all interrupt request flags note in the interrupt routine. if these flags are not cleared (0), subsequent interrupt requests may not be generated. note also that if an interrupt is generated at the same time as a cpu clear operation, that interrupt request flag will not be cleared (0). it is therefore important to confirm that interrupt request flags have been properly cleared (0). note see 18.4.9 can interrupt pending register (ccintp) , 18.4.10 can global interrupt pending register (cgintp) , and 18.4.11 cann interrupt pending register (cnintp) . <3> when a change occurs on the can bus via a setting of the cstp bit in the cstop register while the clock supply to the cpu or peripheral functions is stopped, the cpu can be woken up.
516 user?s manual u14665ej2v0um appendix a register index (1/8) symbol name unit page adcr a/d conversion result register adc 362 adcrh a/d conversion result register h (higher 8 bits) adc 362 adic interrupt control register adc 174 adm1 a/d converter mode register 1 adc 364 adm2 a/d converter mode register 2 adc 366 ads analog input channel specification register adc 366 asim0 asynchronous serial interface mode register 0 uart 331 asim1 asynchronous serial interface mode register 1 uart 331 asis0 asynchronous serial interface status register 0 uart 332 asis1 asynchronous serial interface status register 1 uart 332 bcc bus cycle control register bcu 146 brgc0 baud rate generator control register 0 brg 333 brgc1 baud rate generator control register 1 brg 333 brgck4 baud rate generator output clock selection register 4 brg 354 brgcn4 baud rate generator source clock selection register 4 brg 353 brgmc00 baud rate generator mode control register 00 brg 334 brgmc01 baud rate generator mode control register 01 brg 334 brgmc10 baud rate generator mode control register 10 brg 334 brgmc11 baud rate generator mode control register 11 brg 334 c1ba can1 bus active register fcan 459 c1brp can1 bit rate prescaler register fcan 460 c1ctrl can1 control register fcan 448 c1def can1 definition register fcan 452 c1dinf can1 bus diagnostic information register fcan 463 c1erc can1 error count register fcan 456 c1ie can1 interrupt enable register fcan 457 c1intp can1 interrupt pending register fcan 435 c1last can1 information register fcan 455 c1maskh0 can1 address mask 0 register h fcan 446 c1maskh1 can1 address mask 1 register h fcan 446 c1maskh2 can1 address mask 2 register h fcan 446 c1maskh3 can1 address mask 3 register h fcan 446 c1maskl0 can1 address mask 0 register l fcan 446 c1maskl1 can1 address mask 1 register l fcan 446 c1maskl2 can1 address mask 2 register l fcan 446 c1maskl3 can1 address mask 3 register l fcan 446
appendix a register index user?s manual u14665ej2v0um 517 (2/8) symbol name unit page c1sync can1 synchronization control register fcan 464 c2ba can2 bus active register fcan 459 c2brp can2 bit rate prescaler register fcan 460 c2ctrl can2 control register fcan 448 c2def can2 definition register fcan 452 c2dinf can2 bus diagnostic information register fcan 463 c2erc can2 error count register fcan 456 c2ie can2 interrupt enable register fcan 457 c2intp can2 interrupt pending register fcan 435 c2last can2 information register fcan 455 c2maskh0 can2 address mask 0 register h fcan 446 c2maskh1 can2 address mask 1 register h fcan 446 c2maskh2 can2 address mask 2 register h fcan 446 c2maskh3 can2 address mask 3 register h fcan 446 c2maskl0 can2 address mask 0 register l fcan 446 c2maskl1 can2 address mask 1 register l fcan 446 c2maskl2 can2 address mask 2 register l fcan 446 c2maskl3 can2 address mask 3 register l fcan 446 c2sync can2 synchronization control register fcan 464 canic1 interrupt control register intc 174 canic2 interrupt control register intc 174 canic3 interrupt control register intc 174 canic4 interrupt control register intc 174 canic5 interrupt control register intc 174 canic6 interrupt control register intc 174 canic7 interrupt control register intc 174 ccintp can interrupt pending register fcan 433 cgcs can main clock select register fcan 441 cgie can global interrupt enable register fcan 440 cgintp can global interrupt pending register fcan 434 cgmsr can message search result register fcan 444 cgmss can message search start register fcan 444 cgst can global status register fcan 438 cgtsc can time stamp count register fcan 443 corad0 correction address register 0 cpu 388 corad1 correction address register 1 cpu 388 corad2 correction address register 2 cpu 388 corad3 correction address register 3 cpu 388
appendix a register index 518 user?s manual u14665ej2v0um (3/8) symbol name unit page corcn correction control register cpu 387 corrq correction request register cpu 388 cr00 16-bit capture/compare register 00 rpu 195 cr01 16-bit capture/compare register 01 rpu 196 cr10 16-bit capture/compare register 10 rpu 195 cr11 16-bit capture/compare register 11 rpu 196 cr2 16-bit compare register 2 rpu 231 cr3 16-bit compare register 3 rpu 231 cr4 16-bit compare register 4 rpu 231 cr5 16-bit compare register 5 rpu 231 cr6 16-bit compare register 6 rpu 231 cr70 16-bit capture/compare register 70 rpu 195 cr71 16-bit capture/compare register 71 rpu 196 crc0 capture/compare control register 0 rpu 200 crc1 capture/compare control register 1 rpu 200 crc7 capture/compare control register 7 rpu 200 csib4 variable-length serial setting register csi 352 csic0 interrupt control register intc 174 csic1 interrupt control register intc 174 csic3 interrupt control register intc 174 csic4 interrupt control register intc 174 csim0 serial operation mode register 0 csi 262 csim1 serial operation mode register 1 csi 262 csim3 serial operation mode register 3 csi 262 csim4 variable-length serial control register csi 351 csis0 serial clock selection register 0 csi 263 csis1 serial clock selection register 1 csi 263 csis3 serial clock selection register 3 csi 263 cstop can stop register fcan 437 dbc0 dma byte count register 0 dmac 379 dbc1 dma byte count register 1 dmac 379 dbc2 dma byte count register 2 dmac 379 dbc3 dma byte count register 3 dmac 379 dbc4 dma byte count register 4 dmac 379 dbc5 dma byte count register 5 dmac 379 dchc0 dma channel control register 0 dmac 380 dchc1 dma channel control register 1 dmac 380
appendix a register index user?s manual u14665ej2v0um 519 (4/8) symbol name unit page dchc2 dma channel control register 2 dmac 380 dchc3 dma channel control register 3 dmac 380 dchc4 dma channel control register 4 dmac 380 dchc5 dma channel control register 5 dmac 380 dioa0 dma peripheral i/o address register 0 dmac 377 dioa1 dma peripheral i/o address register 1 dmac 377 dioa2 dma peripheral i/o address register 2 dmac 377 dioa3 dma peripheral i/o address register 3 dmac 377 dioa4 dma peripheral i/o address register 4 dmac 377 dioa5 dma peripheral i/o address register 5 dmac 377 dmaic0 interrupt control register intc 174 dmaic1 interrupt control register intc 174 dmaic2 interrupt control register intc 174 dmaic3 interrupt control register intc 174 dmaic4 interrupt control register intc 174 dmaic5 interrupt control register intc 174 dmas dma start factor expansion register dmac 379 dra0 dma internal ram address register 0 dmac 378 dra1 dma internal ram address register 1 dmac 378 dra2 dma internal ram address register 2 dmac 378 dra3 dma internal ram address register 3 dmac 378 dra4 dma internal ram address register 4 dmac 378 dra5 dma internal ram address register 5 dmac 378 dwc data wait control register bcu 144 ecr interrupt source register cpu 61 egn0 falling edge specification register 0 intc 107, 165 egp0 rising edge specification register 0 intc 106, 165 iic0 iic shift register 0 i 2 c 269, 282 iicc0 iic control register 0 i 2 c 271 iicce0 iic clock expansion register 0 i 2 c 280 iiccl0 iic clock selection register 0 i 2 c 279 iics0 iic status register 0 i 2 c 276 iicx0 iic function expansion register 0 i 2 c 280 ispr in-service priority register intc 175 kric interrupt control register intc 174 krm key return mode register kr 190 mm memory expansion mode register port 74
appendix a register index 520 user?s manual u14665ej2v0um (5/8) symbol name unit page m_conf00 to m_conf31 can message configuration registers 00 to 31 fcan 427 m_ctrl00 to m_ctrl31 can message control registers 00 to 31 fcan 419 m_data000 to m_data317 can message data registers 000 to 317 fcan 423 m_dlc00 to m_dlc31 can message data length registers 00 to 31 fcan 418 m_idh00 to m_idh31 can message id registers h00 to h31 fcan 425 m_idl00 to m_idl31 can message id registers l00 to l31 fcan 425 m_stat00 to m_stat31 can message status registers 00 to 31 fcan 429 m_time00 to m_time31 can message time stamp registers 00 to 31 fcan 421 ncc noise elimination control register intc 177 osts oscillation stabilization time selection register wdt 92, 253 p0 port 0 port 104 p1 port 1 port 108 p10 port 10 port 129 p11 port 11 port 132 p2 port 2 port 112 p3 port 3 port 115 p4 port 4 port 118 p5 port 5 port 118 p6 port 6 port 121 p7 port 7 port 124 p8 port 8 port 124 p9 port 9 port 126 pac port alternate-function control register port 133 pcc processor clock control register cg 89 pf1 port 1 function register port 109 pic0 interrupt control register intc 174 pic1 interrupt control register intc 174
appendix a register index user?s manual u14665ej2v0um 521 (6/8) symbol name unit page pic2 interrupt control register intc 174 pic3 interrupt control register intc 174 pic4 interrupt control register inyc 174 pic5 interrupt control register intc 174 pic6 interrupt control register intc 174 pm0 port 0 mode register port 106 pm1 port 1 mode register port 109 pm10 port 10 mode register port 130 pm11 port 11 mode register port 133 pm2 port 2 mode register port 113 pm3 port 3 mode register port 116 pm4 port 4 mode register port 119 pm5 port 5 mode register port 119 pm6 port 6 mode register port 122 pm9 port 9 mode register port 127 pocs poc status register reset 383 prcmd command register cg 87 prm00 prescaler mode register 00 rpu 203 prm01 prescaler mode register 01 rpu 203 prm10 prescaler mode register 10 rpu 205 prm11 prescaler mode register 11 rpu 205 prm70 prescaler mode register 70 rpu 205 prm71 prescaler mode register 71 rpu 205 psc power save control register cg 91 psw program status word cpu 62 pu10 pull-up resistor option register 10 port 130 rxb0 receive buffer register 0 uart 330 rxb1 receive buffer register 1 uart 330 sc_stat00 to sc_stat31 can status set/clear registers 00 to 31 fcan 431 seric0 interrupt control register intc 174 seric1 interrupt control register intc 174 sio0 serial i/o shift register 0 csi 260 sio1 serial i/o shift register 1 csi 260 sio3 serial i/o shift register 3 csi 260 sio4 variable-length serial i/o shift register csi 349 stic0 interrupt control register intc 174 stic1 interrupt control register intc 174
appendix a register index 522 user?s manual u14665ej2v0um (7/8) symbol name unit page sva0 slave address register 0 i 2 c 269, 282 sys system status register cg 87 tcl20 timer clock selection register 20 rpu 232 tcl21 timer clock selection register 21 rpu 232 tcl30 timer clock selection register 30 rpu 232 tcl31 timer clock selection register 31 rpu 232 tcl40 timer clock selection register 40 rpu 232 tcl41 timer clock selection register 41 rpu 232 tcl50 timer clock selection register 50 rpu 232 tcl51 timer clock selection register 51 rpu 232 tcl60 timer clock selection register 60 rpu 232 tcl61 timer clock selection register 61 rpu 232 tm0 16-bit timer register 0 rpu 194 tm1 16-bit timer register 1 rpu 194 tm2 16-bit counter 2 rpu 231 tm3 16-bit counter 3 rpu 231 tm4 16-bit counter 4 rpu 231 tm5 16-bit counter 5 rpu 231 tm6 16-bit counter 6 rpu 231 tm7 16-bit timer register 7 rpu 194 tmc0 16-bit timer mode control register 0 rpu 197 tmc1 16-bit timer mode control register 1 rpu 197 tmc20 timer mode control register 20 rpu 235 tmc30 timer mode control register 30 rpu 235 tmc40 timer mode control register 40 rpu 235 tmc50 timer mode control register 50 rpu 235 tmc60 timer mode control register 60 rpu 235 tmc7 16-bit timer mode control register 7 rpu 197 tmic00 interrupt control register intc 174 tmic01 interrupt control register intc 174 tmic10 interrupt control register intc 174 tmic11 interrupt control register intc 174 tmic2 interrupt control register intc 174 tmic3 interrupt control register intc 174 tmic4 interrupt control register intc 174 tmic5 interrupt control register intc 174 tmic6 interrupt control register intc 174 tmic70 interrupt control register intc 174
appendix a register index user?s manual u14665ej2v0um 523 (8/8) symbol name unit page tmic71 interrupt control register intc 174 toc0 timer output control register 0 rpu 201 toc1 timer output control register 1 rpu 201 toc7 timer output control register 7 rpu 201 txs0 transmit shift register 0 uart 329 txs1 transmit shift register 1 uart 329 vm45c vm45 control register reset 384 wdcs watchdog timer clock selection register wdt 254 wdtic interrupt control register intc 174 wdtm watchdog timer mode register wdt 176, 255 wtncs watch timer clock selection register wt 247 wtnic interrupt control register intc 174 wtniic interrupt control register intc 174 wtnm watch timer mode control register wt 246
524 user?s manual u14665ej2v0um appendix b instruction set list ? how to read instruction set list mnemonic operand op code operation flag cy ov s z sat this column shows instruction groups. instructions are divided into each instruciton group and described. this column shows instruction mnemonics. this column shows instruction operands (refer to table b-1 ). this column shows instruction operations (refer to table b-3 ). this column shows flag statuses (refer to table b-4 ). this column shows instruction codes (opcode) in binary format. 32-bit instructions are displayed in 2 lines (refer to table b-2 ). instruction group table b-1. symbols in operand description symbol description reg1 general-purpose register (r0 to r31): used as source register reg2 general-purpose register (r0 to r31): mainly used as destination register ep element pointer (r30) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement regid system register number vector 5-bit data that specifies trap vector number (00h to 1fh) cccc 4-bit data that indicates c ondition code
appendix b instruction set list user?s manual u14665ej2v0um 525 table b-2. symbols used for op code symbol description r 1-bit data of code that specifies reg1 or regid r 1-bit data of code that specifies reg2 d 1-bit data of displacement i 1-bit data of immediate data cccc 4-bit data that indicates c ondition code bbb 3-bit data that specifies bit number table b-3. symbols used for operation description symbol description assignment gr[ ] general-purpose register sr[ ] system register zero-extend (n) zero-extends n to word length. sign-extend (n) sign-extends n to word length. load-memory (a,b) reads data of size b from address a. store-memory (a,b,c) writes data b of size c to address a. load-memory-bit (a,b) reads bit b from address a. store-memory-bit (a,b,c) writes c to bit b of address a saturated (n) performs saturated processing of n. (n is 2?s complements). result of calculation of n: if n is n 7fffffffh as result of calculation, 7fffffffh. if n is n 80000000h as result of calculation, 80000000h. result reflects result to a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + add ? subtract || bit concatenation multiply divide and logical product or logical sum xor exclusive logical sum not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift
appendix b instruction set list user?s manual u14665ej2v0um 526 table b-4. symbols used for flag operation symbol description (blank) not affected 0 cleared to 0 set of cleared according to result r previously saved value is restored table b-5. condition codes condition name (cond) condition code ( cccc) c onditional expression description v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ( (s xor ov) or z) = 1 less than or equal signed gt 1111 ( (s xor ov) or z) = 0 greater than signed
appendix b instruction set list user?s manual u14665ej2v0um 527 instruction set list (1/4) flag instruction group mnemonic operand op code operation cy ov s z sat sld.b disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) gr [reg2] sign-extend (load-memory (adr, byte)) sld.h disp8 [ep], reg2 rrrrr1000ddddddd note 1 adr ep + zero-extend (disp8) gr [reg2] sign-extend (load-memory (adr, halfword)) sld.w disp8 [ep], reg2 rrrrr1010dddddd0 note 2 adr ep + zero-extend (disp8) gr [reg2] load-memory (adr, word) ld.b disp16 [reg1], reg2 rrrrr111000rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, byte)) ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 note 3 adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, halfword)) ld.w disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 note 3 adr gr [reg1] + sign-extend (disp16) gr [reg2] load-memory (adr, word)) sst.b reg2, disp7 [ep] rrrrr0111ddddddd adr ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) sst.h reg2, disp8 [ep] rrrrr1001ddddddd note 1 adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) sst.w reg2, disp8 [ep] rrrrr1010dddddd1 note 2 adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) st.b reg2, disp16 [reg1] rrrrr111010rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 note 3 adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) load/store st.w reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 note 3 adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) mov reg1, reg2 rrrrr000000rrrrr gr [reg2] gr [reg1] mov imm5, reg2 rrrrr010000iiiii gr [reg2] sign-extend (imm5) movhi imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + (imm16 || 0 16 ) arithmetic operation movea imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) notes 1. ddddddd is the higher 7 bits of disp8. 2. dddddd is the higher 6 bits of disp8. 3. ddddddddddddddd is the higher 15 bits of disp16.
appendix b instruction set list user?s manual u14665ej2v0um 528 instruction set list (2/4) flag instruction group mnemonic operand op code operation cy ov s z sat add reg1, reg2 rrrrr001110rrrrr gr [reg2] gr [reg2] + gr [reg1] add imm5, reg2 rrrrr010010iiiii gr [reg2] gr [reg2] + sign-extend (imm5) addi imm16, reg1, reg2 rrrrr110000rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] + sign-extend (imm16) sub reg1, reg2 rrrrr001101rrrrr gr [reg2] gr [reg2] ? gr [reg1] subr reg1, reg2 rrrrr001100rrrrr gr [reg2] gr [reg1] ? gr [reg2] mulh reg1,reg2 rrrrr000111rrrrr gr [reg2] gr [reg2] note gr [reg1] note (signed multiplication) mulh imm5, reg2 rrrrr010111iiiii gr [reg2] gr [reg2] note sign-extend (imm5) (signed multiplication) mulhi imm16, reg1, reg2 rrrrr110111rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] note imm16 (signed multiplication) divh reg1, reg2 rrrrr000010rrrrr gr [reg2] gr [reg2] gr [reg1] note (signed division) cmp reg1, reg2 rrrrr001111rrrrr result gr [reg2] ? gr [reg1] cmp imm5, reg2 rrrrr010011iiiii result gr [reg2] ? sign-extend (imm5) arithmetic operation setf cccc, reg2 rrrrr1111110 cccc 0000000000000000 if conditions are satisfied then gr [reg2] 00000001h else gr [reg2] 00000000h satadd reg1, reg2 rrrrr000110rrrrr gr [reg2] saturated (gr [reg2] + gr [reg1]) satadd imm5, reg2 rrrrr010001iiiii gr [reg2] saturated (gr [reg2] + sign- extend (imm5)) satsub reg1, reg2 rrrrr000101rrrrr gr [reg2] saturated (gr [reg2] ? gr [reg1]) satsubi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii gr [reg2] saturated (gr [reg1] ? sign- extend (imm16)) saturated operation satsubr reg1, reg2 rrrrr000100rrrrr gr [reg2] saturated (gr [reg1] ? gr [reg2]) tst reg1, reg2 rrrrr001011rrrrr result gr [reg2] and gr [reg1] 0 or reg1, reg2 rrrrr001000rrrrr gr [reg2] gr [reg2] or gr [reg1] 0 ori imm16, reg1, reg2 rrrrr110100rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] or zero-extend (imm16) 0 and reg1, reg2 rrrrr001010rrrrr gr [reg2] gr [reg2] and gr [reg1] 0 logic operation andi imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] and zero-extend (imm16) 00 note only the lower halfword data is valid.
appendix b instruction set list user?s manual u14665ej2v0um 529 instruction set list (3/4) flag instruction group mnemonic operand op code operation cy ov s z sat xor reg1, reg2 rrrrr001001rrrrr gr [reg2] gr [reg2] xor gr [reg1] 0 xori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii gr [reg2] gr [reg1] xor zero-extend (imm16) 0 not reg1, reg2 rrrrr000001rrrrr gr [reg2] not (gr [reg1]) 0 shl reg1, reg2 rrrrr111111rrrrr 0000000011000000 gr [reg2] gr [reg2] logically shift left by gr [reg1]) 0 shl imm5, reg2 rrrrr010110iiiii gr [reg2] gr [reg2] logically shift left by zero-extend (imm5) 0 shr reg1, reg2 rrrrr1111111 cccc 0000000010000000 gr [reg2] gr [reg2] logically shift right by gr [reg1] 0 shr imm5, reg2 rrrrr010100iiiii gr [reg2] gr [reg2] logically shift right by zero-extend (imm5) 0 sar reg1, reg2 rrrrr111111rrrrr 0000000010100000 gr [reg2] gr [reg2] arithmetically shift right by gr [reg1] 0 logic operation sar imm5, reg2 rrrrr010101iiiii gr [reg2] gr [reg2] arithmetically shift right by zero-extend (imm5) 0 jmp [reg1] 00000000011rrrrr pc gr [reg1] jr disp22 0000011110dddddd ddddddddddddddd0 note 1 pc pc + sign-extend (disp22) jarl disp22, reg2 rrrrr11110dddddd ddddddddddddddd0 note 1 gr [reg2] pc + 4 pc pc + sign-extend (disp22) jump bcond disp9 ddddd1011ddd cccc note 2 if conditions are satisfied then pc pc + sign-extend (disp9) set1 bit#3, disp16 [reg1] 00bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3) store memory-bit (adr, bit#3, 1) clr1 bit#3, disp16 [reg1] 10bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store memory-bit (adr, bit#3, 0) not1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) bit manipulate tst1 bit#3, disp16 [reg1] 11bbb111110rrrrr dddddddddddddddd adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) notes 1. ddddddddddddddddddddd is the higher 21 bits of dip22. 2. dddddddd is the higher 8 bits of disp9.
appendix b instruction set list user?s manual u14665ej2v0um 530 instruction set list (4/4) flag instruction group mnemonic operand op code operation cy ov s z sa t regid = eipc, fepc regid = eipsw, fepsw ldsr reg2, regid rrrrr111111rrrrr 0000000000100000 note sr [regid] gr [reg2] regid = psw stsr regid, reg2 rrrrr111111rrrrr 0000000001000000 gr [reg2] sr [regid] trap vector 00000111111iiiii 0000000100000000 eipc pc + 4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (vector = 00h to 0fh) 00000050h (vector = 10h to 1fh) reti 0000011111100000 0000000101000000 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw rrrrr halt 0000011111100000 0000000100100000 stops di 0000011111100000 0000000101100000 psw.id 1 (maskable interrupt disabled) ei 1000011111100000 0000000101100000 psw.id 0 (maskable interrupt enabled) special nop 0000000000000000 uses 1 clock cycle without doing anything note the op code of this instruction uses the field of reg1 even though the source register is shown as reg2 in the above table. therefore, the meaning of register specification for mnemonic description and op code is different from that of the other instructions. rrrrr = regid specification rrrrr = reg2 specification
user?s manual u14665ej2v0um 531 appendix c index [number] 16-bit compare registers 2 to 6 ------------------------- 231 16-bit counters 2 to 6 ------------------------------------- 231 16-bit timer (tm0, tm1, tm7) --------------------------- 192 16-bit timer (tm2 to tm6) -------------------------------- 230 16-bit timer mode control registers 0, 1, 7 ----------- 197 16-bit timer mode control registers 20 to 60 --------- 235 16-bit timer output control registers 0, 1, 7 ---------- 201 16-bit timer registers 0, 1, 7 ----------------------------- 194 3-wire serial i/o --------------------------------------------- 259 3-wire variable-length serial i/o ------------------------ 348 [a] a/d conversion result register -------------------------- 362 a/d conversion result register h ----------------------- 362 a/d converter ----------------------------------------------- 360 a/d converter mode register 1 ------------------------- 364 a/d converter mode register 2 ------------------------- 366 a16 to a21 -----------------------------------------------------49 ad0 to ad7 ----------------------------------------------------48 ad8 to ad15 --------------------------------------------------49 adcgnd -------------------------------------------------------53 adcr --------------------------------------------------------- 362 adcrh ------------------------------------------------------- 362 adcv dd ---------------------------------------------------------53 address match detection method --------------------- 310 address space ------------------------------------------------64 adic ---------------------------------------------------------- 174 adm1 --------------------------------------------------------- 364 adm2 --------------------------------------------------------- 366 ads ----------------------------------------------------------- 366 adtrg ---------------------------------------------------------46 analog input channel specification register --------- 366 ani0 to ani11 ------------------------------------------------50 arbitration ---------------------------------------------------- 311 area -------------------------------------------------------------68 asck0 ----------------------------------------------------------47 asck1 ----------------------------------------------------------47 asim0, asim1 ---------------------------------------------- 331 asis0, asis1 ----------------------------------------------- 332 astb ------------------------------------------------------------51 asynchronous serial interface -------------------------- 328 asynchronous serial interface mode registers 0, 1 --------------------------------------------- 331 asynchronous serial interface status registers 0, 1 --------------------------------------------- 332 [b] baud rate control function ------------------------------- 488 baud rate generator control registers 0, 1 ---------- 333 baud rate generator mode control registers n0, n1 ----------------------------------------- 334 baud rate generator output clock selection register 4 -------------------------------------------------- 354 baud rate generator source clock selection register 4 -------------------------------------------------- 353 bcc ----------------------------------------------------------- 146 bcu ------------------------------------------------------------- 36 bit stuffing --------------------------------------------------- 484 brgc0, brgc1 ------------------------------------------- 333 brgck4 ----------------------------------------------------- 354 brgcn4 ----------------------------------------------------- 353 brgmcn0, brgmcn1 ----------------------------------- 334 burst read mode-------------------------------------------- 513 bus control function --------------------------------------- 140 bus control pins -------------------------------------------- 140 bus control unit ---------------------------------------------- 36 bus cycle control register ------------------------------- 146 bus hold function ------------------------------------------ 147 bus priority -------------------------------------------------- 156 bus timing --------------------------------------------------- 149 bus width ---------------------------------------------------- 142 byte access ------------------------------------------------- 142 [c] can global interrupt enable register ----------------- 440 can global interrupt pending register ---------------- 434 can global status register ------------------------------ 438 can interrupt pending register ------------------------ 433 can main clock select register ------------------------ 441 can message configuration registers 00 to 31 ---- 427 can message control registers 00 to 31 ------------ 419 can message data length registers 00 to 31 ------ 418 can message data registers n0 to n7 --------------- 423 can message id registers l00 to l31 and h00 to h31 --------------------------------------------- 425 can message search start/result register ---------- 444 can message status registers 00 to 31 ------------- 429 can message time stamp registers 00 to 31 ------ 421
appendix c index user?s manual u14665ej2v0um 532 can module ------------------------------------------------- 401 can ram --------------------------------------------------- 401 can sleep mode ------------------------------------------ 504 can status set/clear registers 00 to 31 ------------- 431 can stop mode -------------------------------------------- 506 can stop register ----------------------------------------- 437 can time stamp count register ------------------------ 443 canic1 to canic7 --------------------------------------- 174 cann address mask a registers l and h ------------ 446 cann bit rate prescaler register ----------------------- 460 cann bus active register -------------------------------- 459 cann bus diagnostic information register ---------- 463 cann control register ------------------------------------ 448 cann definition register --------------------------------- 452 cann error count register ------------------------------- 456 cann information register ------------------------------ 455 cann interrupt enable register ------------------------ 457 cann interrupt pending register ----------------------- 435 cann synchronization control register -------------- 464 canrx1, canrx2 ----------------------------------------- 52 cantx1, cantx2 ------------------------------------------ 52 capture/compare control registers 0, 1, 7 -----------200 capture/compare register n0 ----------------------------195 capture/compare register n1 ----------------------------196 cautions regarding bit set/clear function -------------466 ccintp -------------------------------------------------------433 cg --------------------------------------------------------------- 36 cgcs ---------------------------------------------------------441 cgie ---------------------------------------------------------- 440 cgintp ------------------------------------------------------ 434 cgmss/cgmsr ------------------------------------------ 444 cgst --------------------------------------------------------- 438 cgtsc ------------------------------------------------------- 443 clkout ------------------------------------------------------- 53 clock generation function --------------------------------- 88 clock generator (cg) -------------------------------------- 36 clock output function --------------------------------------- 89 cnba --------------------------------------------------------- 459 cnbrp ------------------------------------------------------- 460 cnctrl ----------------------------------------------------- 448 cndef ------------------------------------------------------- 452 cndinf ------------------------------------------------------ 463 cnerc ------------------------------------------------------- 456 cnie ---------------------------------------------------------- 457 cnintp ------------------------------------------------------ 435 cnlast ------------------------------------------------------ 455 cnmaskla and cnmaskha --------------------------- 446 cnsync------------------------------------------------------ 464 command register -------------------------------------------87 communication command ------------------------------- 398 communication mode ------------------------------------ 392 communication reservation ----------------------------- 314 configuration of message buffers --------------------- 403 connection of unused pins --------------------------------54 corad0 to corad3 ------------------------------------ 388 corcn ------------------------------------------------------- 387 correction address registers 0 to 3 ------------------- 388 correction control register ------------------------------- 387 correction request register ------------------------------ 388 corrq ------------------------------------------------------- 388 cpu -------------------------------------------------------------36 cpu address space -----------------------------------------64 cpu register set ----------------------------------------------59 cpureg -------------------------------------------------------53 cr2 to cr6 ------------------------------------------------- 231 crc0, crc1, crc7 -------------------------------------- 200 crn0 ---------------------------------------------------------- 195 crn1 ---------------------------------------------------------- 196 csi0, csi1, csi3 ------------------------------------------ 259 csi4 ----------------------------------------------------------- 348 csib4 --------------------------------------------------------- 352 csic0, csic1, csic3, csic4 -------------------------- 174 csim4 --------------------------------------------------------- 351 csimn --------------------------------------------------------- 262 csisn --------------------------------------------------------- 263 cstop ------------------------------------------------------- 437 [d] data wait control register -------------------------------- 144 dbc0 to dbc5 --------------------------------------------- 379 dchc0 to dchc5 ----------------------------------------- 380 determination of bus priority ---------------------------- 484 dioa0 to dioa5 ------------------------------------------- 377 dma functions --------------------------------------------- 377 dma byte count registers 0 to 5 ----------------------- 379 dma channel control registers 0 to 5 ----------------- 380 dma internal ram address registers 0 to 5 -------- 378 dma peripheral i/o address registers 0 to 5 ------- 377 dmaic0 to dmaic5 --------------------------------------- 174 dma start factor expansion register ------------------ 379 dmas --------------------------------------------------------- 379 dra0 to dra5 --------------------------------------------- 378 dstb ------------------------------------------------------------51 dwc ---------------------------------------------------------- 144 [e]
appendix c index user?s manual u14665ej2v0um 533 ecr -------------------------------------------------------------61 edge detection function ---------------------------------- 178 egn0 -------------------------------------------------- 107, 165 egp0 --------------------------------------------------- 106, 165 eipc -------------------------------------------------------------61 eipsw ----------------------------------------------------------61 ensuring data consistency ------------------------------ 512 ep flag -------------------------------------------------------- 181 error control function -------------------------------------- 485 error detection ---------------------------------------------- 310 exception trap ---------------------------------------------- 181 extension code --------------------------------------------- 310 external expansion mode ----------------------------------74 external memory ---------------------------------------------72 external wait function ------------------------------------- 145 [f] fcan controller -------------------------------------------- 400 falling edge specification register 0 ----------- 107, 165 fepc ------------------------------------------------------------61 fepsw ---------------------------------------------------------61 flash memory ----------------------------------------------- 390 flash memory control ------------------------------------- 397 flash memory programming mode -------------- 63, 397 [g] general-purpose registers ---------------------------------60 gnd0 to gnd2 -----------------------------------------------53 [h] halfword access -------------------------------------------- 142 halt mode ----------------------------------------------------94 hardware start ---------------------------------------------- 360 hldak ----------------------------------------------------------51 hldrq ---------------------------------------------------------51 [i] i 2 c bus -------------------------------------------------------- 266 i 2 c bus mode ----------------------------------------------- 266 i 2 c interrupt request --------------------------------------- 291 ic -----------------------------------------------------------------53 id --------------------------------------------------------------- 175 idle mode -----------------------------------------------------97 idle state insertion function ------------------------------ 146 iic clock expansion register 0 -------------------------- 280 iic clock selection register 0 ---------------------------- 279 iic control register 0 --------------------------------------- 271 iic function expansion register 0 ----------------------- 280 iic shift register 0 ------------------------------------269, 282 iic status register 0 ---------------------------------------- 276 iic0 ------------------------------------------------------269, 282 iicc0 ---------------------------------------------------------- 271 iicce0 -------------------------------------------------------- 280 iiccl0--------------------------------------------------------- 279 iics0----------------------------------------------------------- 276 iicx0----------------------------------------------------------- 280 illegal op code ---------------------------------------------- 181 images --------------------------------------------------------- 65 in-service priority register ------------------------------- 175 initialization processing----------------------------------- 491 intc ------------------------------------------------------------ 36 internal peripheral i/o area ------------------------------- 71 internal ram area ------------------------------------------- 70 internal registers of fcan controller ------------------ 403 internal rom/flash memory area ------------------------ 68 interrupt conditions ---------------------------------------- 514 interrupt control register --------------------------------- 172 interrupt controller ------------------------------------------- 36 interrupt disable flag -------------------------------------- 175 interrupt request signal generator --------------------- 270 interrupt source register ----------------------------------- 61 interrupt status saving register --------------------------- 61 interrupt/exception processing function ------------- 157 interrupts that occur for fcan controller------------- 514 interrupts that occur for global can interface ------ 514 interval timer mode --------------------------------------- 252 intp0 to intp6 ---------------------------------------------- 46 ispr ---------------------------------------------------------- 175 [k] key interrupt function ------------------------------------- 190 key return mode register -------------------------------- 190 kr0 to kr7 --------------------------------------------------- 52 kric ---------------------------------------------------------- 174 krm ----------------------------------------------------------- 190 [l] lben ----------------------------------------------------------- 50 list of fcan registers ------------------------------------ 404 low power consumption mode ------------------------ 373 [m] m_conf00 to m_conf31 ----------------------------- 427 m_ctrl00 to m_ctrl31 ------------------------------ 419 m_datan0 to m_datan7 ------------------------------ 423 m_dlc00 to m_dlc31 ---------------------------------- 418
appendix c index user?s manual u14665ej2v0um 534 m_idl00 to m_idl31, m_idh00 to m_idh31 ----- 425 m_stat00 to m_stat31 ------------------------------- 429 m_time00 to m_time31 -------------------------------- 421 mac ---------------------------------------------------------- 401 main system clock oscillator ------------------------------ 88 mask function -----------------------------------------------472 maskable interrupts ----------------------------------------166 memory block function ------------------------------------143 memory boundary operation condition ---------------156 memory expansion mode register ---------------------- 74 memory map -------------------------------------------------- 67 message formats ------------------------------------------ 475 message processing ---------------------------------------471 mm -------------------------------------------------------------- 74 multi-cast -----------------------------------------------------484 multiple interrupt servicing --------------------------------184 multiple masters --------------------------------------------484 [n] ncc ------------------------------------------------------------177 nmi -------------------------------------------------------------- 46 nmi status saving register -------------------------------- 61 noise elimination -------------------------------------------176 noise elimination control register ----------------------177 non-maskable interrupt -----------------------------------160 normal operation mode ------------------------------------ 63 npb interface ---------------------------------------------- 401 number of access clocks ------------------------------- 141 [o] off-board programming -----------------------------------391 on-board programming -----------------------------------391 operation modes -------------------------------------------- 63 oscillation stabilization time -----------------------------101 oscillation stabilization time selection register ------------------------------- 92, 253 osts ---------------------------------------------------- 92, 253 [p] p0 --------------------------------------------------------------104 p00 to p07 ---------------------------------------------------- 46 p1 --------------------------------------------------------------108 p10 -------------------------------------------------------------129 p10 to p15 ---------------------------------------------------- 46 p100 to p107 ------------------------------------------------- 52 p11 -------------------------------------------------------------132 p110 to p117 ------------------------------------------------- 52 p2 --------------------------------------------------------------112 p20 to p27 -----------------------------------------------------47 p3 -------------------------------------------------------------- 115 p30 to p34 -----------------------------------------------------48 p4 -------------------------------------------------------------- 118 p40 to p47 -----------------------------------------------------48 p5 -------------------------------------------------------------- 118 p50 to p57 -----------------------------------------------------49 p6 -------------------------------------------------------------- 121 p60 to p65 -----------------------------------------------------49 p7 -------------------------------------------------------------- 124 p70 to p77 -----------------------------------------------------50 p8 -------------------------------------------------------------- 124 p80 to p83 -----------------------------------------------------50 p9 -------------------------------------------------------------- 126 p90 to p96 -----------------------------------------------------50 pac ----------------------------------------------------------- 133 pc ---------------------------------------------------------------60 pcc -------------------------------------------------------------89 periods in which interrupts are not acknowledged- 187 peripheral i/o registers -------------------------------------78 pf1 ------------------------------------------------------------ 109 pic0 to pic6 ------------------------------------------------ 174 pin functions --------------------------------------------------38 pin i/o buffer power supply -------------------------------54 pin i/o circuit type -------------------------------------------54 pm0 ------------------------------------------------------------ 106 pm1 ------------------------------------------------------------ 109 pm10 ---------------------------------------------------------- 130 pm11 ---------------------------------------------------------- 133 pm2 ------------------------------------------------------------ 113 pm3 ------------------------------------------------------------ 116 pm4 ------------------------------------------------------------ 119 pm5 ------------------------------------------------------------ 119 pm6 ------------------------------------------------------------ 122 pm9 ------------------------------------------------------------ 127 poc status register ---------------------------------------- 383 pocs ---------------------------------------------------------- 383 ports -------------------------------------------------------------37 port 0 ---------------------------------------------------------- 104 port 0 mode register -------------------------------------- 106 port 1 ---------------------------------------------------------- 108 port 1 function register ----------------------------------- 109 port 1 mode register -------------------------------------- 109 port 10 -------------------------------------------------------- 129 port 10 mode register ------------------------------------- 130 port 11 -------------------------------------------------------- 132 port 11 mode register ------------------------------------- 133 port 2 ---------------------------------------------------------- 112
appendix c index user?s manual u14665ej2v0um 535 port 2 mode register -------------------------------------- 113 port 3 ---------------------------------------------------------- 115 port 3 mode register -------------------------------------- 116 port 4 ---------------------------------------------------------- 118 port 4 mode register -------------------------------------- 119 port 5 ---------------------------------------------------------- 118 port 5 mode register -------------------------------------- 119 port 6 ---------------------------------------------------------- 121 port 6 mode register -------------------------------------- 122 port 7 ---------------------------------------------------------- 124 port 8 ---------------------------------------------------------- 124 port 9 ---------------------------------------------------------- 126 port 9 mode register -------------------------------------- 127 port alternate-function control register --------------- 133 portgnd------------------------------------------------------53 portv dd -------------------------------------------------------53 power save control register -------------------------------91 power save functions ---------------------------------------93 power-on-clear operation--------------------------------- 383 prcmd ---------------------------------------------------------87 prescaler mode registers 00, 01 ----------------------- 203 prescaler mode registers m0, m1 --------------------- 205 prioritization of message buffers during receive comparison ------------------------------------------------ 510 priorities of interrupts and exceptions----------------- 184 priority control ---------------------------------------------- 184 prm00, prm01 -------------------------------------------- 203 prmm0, prmm1 ------------------------------------------ 205 processor clock control register -------------------------89 program counter ---------------------------------------------60 program register set ----------------------------------------60 program status word ----------------------------------------62 programmable wait function ---------------------------- 144 programming environment ------------------------------ 391 programming method ------------------------------------- 397 protcol --------------------------------------------------------- 474 protcol mode function ------------------------------------- 474 psc -------------------------------------------------------------91 psw -------------------------------------------------------------62 pu10 ---------------------------------------------------------- 130 pull-up resistor option register 10 --------------------- 130 [r] r/w --------------------------------------------------------------51 ram -------------------------------------------------------------36 receive buffer registers 0, 1 ---------------------------- 330 receive setting ---------------------------------------------- 503 receive shift registers 0, 1 ------------------------------ 329 reception of data frames -------------------------------- 510 reception of remote frames----------------------------- 511 recommended use of address space ----------------- 75 regulator ---------------------------------------------------- 385 reset --------------------------------------------------------- 53 reset function ---------------------------------------------- 382 response time ---------------------------------------------- 187 rising edge specification register 0 ------------106, 165 rom ------------------------------------------------------------ 36 rom correction function --------------------------------- 386 rules for correct setting of baud rate ---------------- 507 rx0, rx1 ---------------------------------------------------- 329 rxb0, rxb1 ------------------------------------------------ 330 rxd0 ----------------------------------------------------------- 47 rxd1 ----------------------------------------------------------- 47 [s] sar ----------------------------------------------------------- 362 sck0, sck1 -------------------------------------------------- 46 sck3, sck4 -------------------------------------------------- 47 scl0 ------------------------------------------------------------ 47 sda0 ----------------------------------------------------------- 46 sc_stat00 to sc_stat31 ---------------------------- 431 sequential data read -------------------------------------- 512 serial clock counter --------------------------------------- 270 serial clock selection register n ----------------------- 263 serial i/o shift register n---------------------------------- 260 serial interface function ---------------------------------- 259 serial operation mode register n ---------------------- 262 seric0, seric1 ------------------------------------------ 174 si0, si1 -------------------------------------------------------- 46 si3, si4 -------------------------------------------------------- 47 single-chip mode -------------------------------------------- 63 sion ----------------------------------------------------------- 260 sio4 ---------------------------------------------------------- 349 slave address register 0 ---------------------------269, 282 so latch ------------------------------------------------------ 269 so0, so1 ------------------------------------------------------ 46 so3, so4 ------------------------------------------------------ 47 software exception ---------------------------------------- 179 software start ----------------------------------------------- 360 software stop mode -------------------------------------- 99 specific registers -------------------------------------------- 85 standby function ------------------------------------------- 347 start condition ---------------------------------------------- 284 start facter settings ---------------------------------------- 381 stic0, stic1 ----------------------------------------------- 174 stop condition ---------------------------------------------- 288
appendix c index user?s manual u14665ej2v0um 536 subsystem clock oscillator -------------------------------- 88 successive approximation register --------------------362 sva0 ---------------------------------------------------269, 282 sys ------------------------------------------------------------- 87 system register set ----------------------------------------- 61 system status register ------------------------------------- 87 [t] tcl20 to tcl60 --------------------------------------------232 tcl21 to tcl61 --------------------------------------------232 ti00, ti01, ti10, ti11, ti70 ------------------------------ 52 ti2, ti3, ti4, ti5, ti71 ------------------------------------- 48 time stamp function ---------------------------------------468 timer clock selection registers 20 to 60 --------------232 timer clock selection registers 21 to 61 --------------232 timer/counter function ------------------------------------192 tm0, tm1, tm7 --------------------------------------192, 194 tm2 to tm6 -------------------------------------------230, 231 tmc0, tmc1, tmc7 --------------------------------------197 tmc20 to tmc60 ------------------------------------------235 tmic00 -------------------------------------------------------174 tmic01 -------------------------------------------------------174 tmic10 -------------------------------------------------------174 tmic11 -------------------------------------------------------174 tmic2 to tmic6 --------------------------------------------174 tmic70, tmic71 --------------------------------------------174 to0, to1, to7 ---------------------------------------------- 52 to2, to3, to4, to5 --------------------------------------- 48 toc0, toc1, toc7 ---------------------------------------201 transfer completion interrupt request -----------------377 transfer direction specification --------------------------286 transmit setting ---------------------------------------------502 transmit shift registers 0, 1 ------------------------------329 txd0 ----------------------------------------------------------- 47 txd1 ----------------------------------------------------------- 47 txs0, txs1 --------------------------------------------------329 [u] uart0, uart1 ---------------------------------------------328 uben ----------------------------------------------------------- 51 [v] variable-length serial control register 4 -------------- 351 variable-length serial i/o shift register 4 ------------- 349 variable-length serial setting register 4 -------------- 352 v dd0 --------------------------------------------------------------53 vm45-------------------------------------------------------------48 vm45 control register -------------------------------------- 384 vm45c--------------------------------------------------------- 384 v pp ---------------------------------------------------------------53 [w] wait ------------------------------------------------------------52 wait function ------------------------------------------------ 144 wait signal---------------------------------------------------- 289 wake-up controller ---------------------------------------- 269 wakeup function ------------------------------------------- 313 watch timer clock selection register ------------------ 247 watch timer function -------------------------------------- 244 watch timer mode control register -------------------- 246 watchdog timer clock selection register ------------- 254 watchdog timer function --------------------------------- 251 watchdog timer mode ------------------------------------ 252 watchdog timer mode register ------------------ 176, 255 wdcs -------------------------------------------------------- 254 wdtic -------------------------------------------------------- 174 wdtm ------------------------------------------------- 176, 255 word access ------------------------------------------------ 142 wraparound of cpu address space --------------------66 write/read time ---------------------------------------------- 391 writing with flash programmer ------------------------- 391 wtncs ------------------------------------------------------- 247 wtnic -------------------------------------------------------- 174 wtniic-------------------------------------------------------- 174 wtnm --------------------------------------------------------- 246 [x] x1 ----------------------------------------------------------------53 x2 ----------------------------------------------------------------53 xt1 --------------------------------------------------------------53 xt2 --------------------------------------------------------------53
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we?ve taken, you may encounter problems in the documentation. please complete this form whenever you?d like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 taiwan nec electronics taiwan ltd. fax: +886-2-2719-5951 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 01.2 name company from: tel. fax facsimile message


▲Up To Search▲   

 
Price & Availability of UPD70F3079YGF-3BA

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X